To address leakage, or power drain, which has become
increasingly problematic as transistor dimensions continue to
shrink, Texas Instruments said it will integrate a “high-k” value
material within the transistors in its high performance 45nm
chips.
With its approach, TI believes it can reduce leakage by more
than 30 times per unit area as compared with commonly used silicon
dioxide (SiO2) gate dielectrics.
In addition, TI said its high-k option offers compatibility,
reliability and scalability for high volume, high performance and
low power semiconductor solutions through the 45nm and 32nm process
nodes.
Dr. Hans Stork, CTO of TI reminded that TI has been at the
forefront of hafnium-based R&D for nearly a decade, and the
company is confident that its high-k choice overcomes the
technological hurdles faced through continued digital CMOS scaling
and the transition to smaller process geometries.
Last June, TI unveiled details of its 45nm process that it says
will double output per wafer through use of 193nm immersion
lithography. Through a number of techniques, the company said it
will also achieve a 30 per cent increase in performance of its SoC
processors, while reducing power consumption 40 per cent.
The company expects to sample a 45nm wireless product this year,
with qualified production starting by mid-2008, with the high-k
dielectrics to be added in later versions of the 45nm process for
the highest performance products.
Several 45nm recipes are purported to address end-product
requirements and provide options for creating optimised designs
including a low power offering that extends battery life in
portable products, while delivering the necessary performance for
advanced multimedia functionality in tightly integrated SoC
designs.
A mid-range process supports TI DSPs and the high performance
Asic library for communications infrastructure products, and a
third, highest performance 45nm process option supports MPU-class
performance and is expected to be the first process to integrate
the high-k material.
TI confirmed it will leverage a chemical vapor deposition (CVD)
process to deposit hafnium silicon oxide (HfSiO) followed by
reaction with a downstream nitrogen plasma to form HfSiON.
The benefits of hafnium-based dielectrics have been widely
recognized for the impact on leakage; implementation has previously
presented several hurdles, including electrical compatibility with
standard CMOS processes, as well as challenges in matching the
carrier mobility and threshold voltage stability that SiO2-based
gate dielectrics have previously delivered.
However, TI believes that by implementing the nitrided CVD
technique, it is able to solve the leakage issue without
degradation of the other key parameters that customers have come to
expect from SiO2-based gate dielectrics. TI asserts that its
approach reduces leakage significantly over any of the SiO2-based
material options.
TI said the nitridation of CVD HfSiON film also delivers the
scalability that supports the performance, power consumption and
gate length requirements outlined through the 32nm node.
Through a modular addition to the typical CMOS gate stack
process, HfSiON integration has been demonstrated, offering
mobility that is 90 per cent of the silicon dioxide universal
mobility curve, with effective oxide thicknesses below 1-nm. These
results were accomplished without sacrificing reliability or adding
significant cost to the CMOS process, the company noted. Precise
tuning of the film composition, tight controls, and high throughput
also make HfSiON suitable for high volume manufacturing
TI added that its research includes the composition, process
optimisation and characterization of HfSiON gate dielectric films,
and these efforts are compatible with its 45nm metal gate
strategy.
Intel and IBM have been at the forefront of 45-nm process
development, waging a battle in the market with technical specs or
lack thereof, depending on which party is talking.
In January, both companies on the same day revealed they would
embrace high-k metal gates for 45nm.
At this week's VLSI Symposium in Japan, IBM is expected to
present a paper on its 45nm outlook, including high-k metal gate.
In February, IBM said it would roll out a 45nm immersion
lithography process by end of the year, while Intel is waiting
until the cost and performance benefits are more obvious, the
company told Electronic News.
Industry supports are anxiously awaiting IBM’s full disclosure
on its full k solution, including high-k, pmos and nmos data, along
with results of working chips and performance data. Other industry
players including AMD and NEC are also working toward the full k
solution.
The real question for customers is which company will have the
complete offering first, and for which products. There are still
many pieces to the puzzle that need to be fleshed out.