By Michael Santarini, Senior Editor - EDN, 12/10/2006

With the emergence of IC foundries in Taiwan, Singapore, and mainland China over the last decade and an abundance of relatively inexpensive engineering resources in India, eastern Europe, and mainland China now available, ASIC and SOC (system-on-chip) design is becoming a global effort.

Indeed, it is difficult to find a company that has not established an offshore design center or is not tapping into a foreign location for some type of assistance, whether it is for manufacturing a chip at a Taiwanese fab, design services in India, or IP (intellectual-property) creation in Israel.

An abundance of global resources is available to IC companies. But that abundance brings numerous challenges that management must face in organizing ASIC- and SOC-design efforts to get chips to market on time. Global efforts require managers to negotiate different time zones, language, cultures, holiday schedules, licensing, and infrastructure.

Beyond these issues, design managers are coming up with unique strategies to ensure that designs meet goals and are on time. To complete designs on time, they use localized R&D with global manufacturing, global-platform-based design, and global-design factories.

Localized R&D

Raza Microelectronics is perhaps the epitome of the localized R&D company.

A Silicon Valley start-up that has raised approximately $120 million in venture-capital funding, Raza Micro is producing complex 300 million-transistor SOCs for the 3G base-station and security-appliance markets. The company has resisted the temptation to tap into relatively less expensive offshore hardware-engineering resources. It has even resisted the appeal of nationally distributed design teams.

"At Raza Micro's XLR-processor line, we don't develop typical ASICs, so the model for a typical ASIC doesn't work for us," says Nazar Zaidi, vice president of engineering for scalable processors at Raza. "We need to have tight integration of the various aspects of the design. That means we must have close geometric proximity of the different types of IC designers."

All of Zaidi's hardware-design team is in California.

"Having design teams split further exacerbates the time-to-market problem," Zaidi says.

"If we were dealing with standard, proven methodologies, processes, and everything else, then we could think about separating and farming out work here and there, but, more often than not, we're trying to solve a difficult technical challenge as we are building the chip. We don't have all the answers when we start out. We expect to find the answers as we are working on it, so there is not a lot of time to create a detailed methodology and flows that we can hand off to an offsite team."

A significant percentage of Raza Micro's designs require full-custom techniques, though the company mixes in more automated-ASIC methods and IP when it can. "What we think may be custom on day one may change based on how the design evolves," Zaidi says. In the course of a given chip-design project, the size of a team varies from 20 to 65 engineers, and the team grows to its largest during layout.

The company has small groups that specialize in one aspect of the design-logic design, verification, or layout and DFM (design for manufacturing), but employees with broad repertoires are key.

"In a start-up, you have to have individuals that can wear many hats; those folks tend to be the glue of the team," Zaidi says. "They are the ones that make sure that information transfers accurately from one group to the other because they understand the issues on both sides."

Although Raza's hardware team is in one location, the company has a software-development group in India.

"Software design starts typically a couple of months after hardware design begins," Zaidi says. "There are some severe limitations. We run a lot of applications on RTL [register-transfer level] long before we tape out the chip. We have performance and reference models in which we run large blocks of field software code to see how parts of the machine will behave and react."

The company uses TSMC (Taiwan Semiconductor Manufacturing Co,) to manufacture its silicon and gets the foundry involved early in the process.

"Our chip was one of the first high-performing processors TSMC fabbed in its 90-nm process," says Zaidi, noting that Raza is currently targeting its next-generation ICs at TSMC, as well, but Zaidi declines to disclose at which node. Raza Micro also buys IP from various sources. The company holds a MIPS-processor-architecture license but does not buy predefined cores from MIPS. The company also acquires commodity IP for standard functions.

"Designing a new UART is not necessarily the value we provide in the chip, so we acquire some standard IP from vendors," says Zaidi.

As Raza Micro grows, the company puts more effort into global design, depending on the complexity of the design.

"There are capable resources in China, India, and eastern Europe," says Zaidi. "When you get into the second or third level of derivatives, then maybe you can give a full design to those folks. If you outsource, you should outsource the whole thing. You don't want to draw boundaries between glue logic, circuits, physical design, and all that; you have to hand it off as a full-blown project."

Platform approach

Whereas Raza Micro uses a localized R&D design effort with globalized software design and manufacturing, publicly held system company Pixelworks has embraced global design by employing a platform-based approach. Chief Technical Officer and Vice President of Engineering Richard Tobias manages a few hundred engineers in several design centers in North America, Asia, Western Europe, and Eastern Europe. The company has four product lines, with engineering groups for each line producing two to four chips per year.

"Most chips are derivatives," says Tobias. "Few chips are developed in just one location. IP from groups around the world come together in one design center to create a system chip."

Pixelworks has adapted a concise platform-based approach for its IC designs to make sure it just isn't slapping disparate blocks together in the 11th hour of the design process. It's an approach Tobias helped devise at his previous company, Toshiba, which developed the SOCMosaic platform, and is an approach that TI has successfully employed with its OMAP (Open Multimedia Applications Platform) product.

"In the platform approach, the platform architecture is the same for every SOC, but some of its chips are not really SOCs," says Tobias. "Every chip family is its own market-segment-oriented product line. You can use the generic platform to generate any SOC, but you need market-specific IP, software, systems knowledge, and so forth to create a specific chip."

An SOC-block-based development architecture, such as a platform, allows global teams to simultaneously develop designs and to work on the same chip.

"For complicated chips, you need to find expertise for subfunctions in many parts of the world," Tobias says.

"You then need to combine the IP they create into a bigger system—boards, chips, and software. You need to create an architecture that makes it easy to do this co-development without a huge amount of interaction between the groups. So, we've created a system architecture that predefines the interfaces, thus allowing the teams to interact only across this API [application-programming interface] or chip interface, and thus we can quickly create systems."

The company's architecture group develops each product line and platform.

"This group creates the overall architecture and creates the methodologies and tool flows to design in the architecture," says Tobias. "This sort of architecture is generic for SOCs. Each product line then has a system architecture. A local architect with the local chip team leads this architecture development, but the global architecture group does most of the software development because most of the company's software is portable to every platform."

Although the company has design teams focus on particular projects, the verification team is a separate organization but has people in every design center. "Most system verification is in a single site, but unit verification typically happens closer to the developer," says Tobias. "We try to keep unit tests near the unit developer and system tests near the system developer."
 
The company collocates most firmware development with the hardware teams, but system-software development typically occurs at other sites. "We develop higher level application software as subfunctions in a way that allows worldwide development," says Tobias. The biggest key to employing the global-platform-based approach is having great site management, he says. "You need to pick global leaders. Your leadership can be in many countries, but they need to be special people who took the time to understand many worldwide cultures. We also have global program managers with the same sort of leadership skills," Tobias says.

To keep track of designs, Pixelworks has a program office and has created a standard set of methodologies and flows to manage projects. A set of standard reports sums up these projects so that upper management can track all programs—both global and local—in the organization. The company has also established a standard EDA flow across its organization based on best-in-class point tools from EDA vendors. Tobias notes that EDA companies could further help his organization by creating better program-management tools and EDA-database-management tools that work worldwide.

Pixelworks develops most of its own IP but sometimes procures it from IP vendors. However, the company tries to steer clear of IP licensing that demands royalties. "We have great ideas from our multinational teams. We need teams that are big enough to allow for interaction and with enough engineering disciplines that the group can create ideas. Also, communication is key. Creating a highly communicative environment involves using tools from conference calls, videoconferences, screen sharing, and database sharing."

Whereas Raza Microelectronics prefers to have all its hardware engineers in one location and Pixelworks uses engineering talent around the globe in the framework of a platform approach, Open Silicon has introduced a highly automated, highly disciplined, "cookie-cutter" methodology that it can apply to design centers around the globe.

Global design factory

Unlike Raza and Pixelworks, Open Silicon is not a systems company. Instead, it is a fabless-ASIC vendor, a new breed that works with foundries to produce silicon using RTL or netlist hand-offs (see ASIC houses change with the global tide). It then performs package design and testing.

There are a handful of fabless-ASIC vendors in the market today, but Open Silicon differentiates itself by employing a highly disciplined design model that it believes exceeds global boundaries. The company's co-founder, president, and chief executive officer, Naveed Sherwani, PhD, was formerly the general manager of Intel's now-defunct ASIC business; through that experience and others, he derived Open Silicon's unique model.

"In the three years at Intel, we had 28 design wins, and in the three years since we've founded Open Silicon, we have 70 design wins," says Sherwani. "I believe that is the most that any ASIC vendor produced in recent years."

The company's revenue will grow this year to nearly triple that of last year. The company owes its success in a small part to hiring relatively inexpensive labor in India and largely to enforcing great discipline and parameters on the types of ASICs the company will design and even more discipline in how it designs them.

The company manufactures only relatively simple, mainstream ASICs. It does not bother with complex analog- or mixed-signal designs or super-high-performance digital designs in the most advanced process geometries.

The company engages only those projects that meet its "22-point criteria." For example, one criterion is that the design team can implement the design in 180- to 90-nm process geometries; another is that the design must have no more than 20 million gates. The company has similar criteria for hierarchy, amount of memory, and number of IP blocks in a design. The company has developed and enforces a strict internal methodology, using one tool flow across all design groups (Figure 1).

The company divided its engineering force into DCUs (design-center units). "It is a simple concept that simply states: 'Constrain yourself to doing certain types of ASICs,'" says Sherwani. "We've created a systematic, methodical flow in which the steps don't change; hence, over time, you can automate as much as possible. It allows us to create multiple such DCUs around the world, so we don't have to worry that designers in Israel are doing a design differently from those in India. You have a cookie-cutter DCU that you can put anywhere in the world."

A DCU at Open Silicon comprises five or six engineers (Figure 2). Each engineer specializes in a discipline of layout or physical verification. Sherwani notes that, in large ASIC groups, "fiefdoms" often develop within engineering staffs, and designers form into an A Team, a B Team, and a C Team. To avoid this scenario, Sherwani rotates engineers within DCUs.

The company has a profile of the types of engineers it will hire, typically tapping into second- and third-tier universities in India to find overlooked talent. The company has also developed its own IC Catalyst management software, which allows it to standardize the design from the start of the process to delivery of a prototype. IC Catalyst handles all the processes, schedules, cost, people, and tool issues. The tool controls versions of EDA software, too. The company has derived a point-tool flow from the various EDA-vendor flows and has strict rules on their use.

Although Open Silicon can implement DCUs anywhere in the world, the company resists increasing its staff and wants to make its engineering staff more productive by increasing the amount of automation in its organization and tool flow.

"We're focused on optimizing existing designs rather than initiating new, labor-intensive designs," says Sherwani.

"You'll not see our head count go from 100 people to 5000 people. The idea is to use the optimized methods to do more designs with the same number of people. We will grow, and we plan on investing more in our current infrastructure so that we become more productive. That rapid growth model—one design with 100 people and the next design with 400 people and the next with 800 people—is a formula for death. When I was at Intel, we were using 1200 people for a single ASIC, and 400 people were doing nothing but coordinating other people."

Sherwani offers six rules the company follows for global design (see Guide to global design).

Overall, chip-design companies are employing many innovative strategies to leverage global resources. Although some debate exists about whether companies can effectively create highly complex ASICs and SOCs—R&D-class designs that break new ground in performance or features—on a global scale, everyone concurs that worldwide engineering resources and talent are growing, and new market opportunities are on the horizon.

It will be interesting to watch what new methodologies develop as China and India mature and make the inevitable transition from centers of low-cost manufacturing to powerhouses in IC-design innovation. If you don't believe that this transition will take place, visit Shanghai; it will take you less than a day to realize that it already has.

Further information

Infineon TechnologiesASIC Design and Security Group

Open Silicon

Pixelworks

Raza Microelectronics