Simplifying memory subsystem design reduces the total product cost and improves the time to market. For an embedded system designer, much of the memory architecture design effort is spent on selecting the multiple memories and chipsets that will satisfy the system requirements, including functionality, performance, cost, power consumption, form factor and schedule.

In addition, the chipset designer spends much time designing many memory controllers and interfaces that connect to the chipset. A ready to use memory subsystem that unifies and manages the various required memory types and interfaces can dramatically reduce the memory subsystem design, development time and the final product cost.
In today’s embedded systems, multiple types of memories are required for system boot code, OS and application code and user data. Some of these memories come in volatile and nonvolatile flavours.

For example, a system or chipset designer may include, low to high density NOR flash for boot code or execute in place (XIP) application and system code, NAND flash for data, and RAM for data and/or code during execution. A complete system to simplify the designer’s task would have to include all types of memories and interfaces that the designer would need.

Ever changing memory technology and interface

Memory technology is constantly evolving to meet the product requirements in the embedded market. In recent years, many volatile and nonvolatile technologies introduced have addressed the speed, size and cost requirements of embedded systems and applications.
Volatile technologies still in use include SRAM, DRAM, PSRAM, DDR DRAM, and DDR2 DRAM, which use multiple, different interfaces.

In the non-volatile memory arena, we see technologies such as ROM, EPROM, EEPROM, NOR flash, and NAND flash which address various parts of the market and now PCRAM (phase-change memory, PCM, PRAM), FRAM (ferroelectric RAM, FeRAM) and RRAM (resistive RAM) are around the corner.
Unfortunately, most of these technologies have their own specific interface and functionality that do not allow an easy transition from one to another.

For example SRAM and PSRAM have very similar interfaces and so does the DDR DRAM family. However, changing from SRAM to DRAM requires an interface and controller change.
ROM, NOR flash, and NAND flash have very different interfaces and capabilities. NOR flash is well suited for predominantly read operations, and NAND flash can perform much faster write operations.

In many embedded applications, both of these capabilities are required, making memory subsystem design more complex. Furthermore, to take advantage of NAND capacity and to provide XIP capability, the complexity of the memory subsystem is increased by adding some type of RAM. Hence, the system and chipset designers have to deal with a number of different memories for a variety of reasons.

For every system design requiring multiple types of memory, multiple memory controllers and interfaces must be designed and redesigned as the technology changes.

Today, in many embedded devices one can find SRAM or DRAM used as main memory, NOR for boot and application code, and NAND as storage for data, and often code as well. For every memory type used in the system, an accompanying memory controller and interface must be designed. Unfortunately, these interfaces and controllers often have to be redesigned as the technology changes or new memory types are introduced.

Design stability with memory technology changes

It would be nice if the system designers dealt with a single memory package that provided and managed all memory types needed with a single interface. And one that would simplify the design task, reduce the design and redesign cost, and improve the time to market.
This is possible to a large extent. Building a black box with a single interface that includes various types of memories that most embedded systems need would be one way to tackle the problem.

The host would provide the required information such as read or write operations, address, memory type or number and perhaps delivery speed, and the black box would interpret the information, generate the proper sequence of commands, access the appropriate memory, and complete the requested operation.

The factors that are important in memory subsystem design are bandwidth, latency, power consumption, cost and form factor.

With every design, these factors are traded off against each other and against the development schedule. These trade offs require the system architect to investigate various alternatives in great detail.

The system architect can save much time and effort if memory subsystems that satisfy system requirements are readily available. This would also afford the chipset designers the luxury of designing to a single interface that can interact with and manage all required memory types.

One for all

An ideal answer would be the Swiss army knife equivalent of memory. System companies would be able to buy what is needed, and configure it for their application. There would be no need to design multiple memory types, interfaces, and controllers.

System companies would only need to shop around for the managed memory subsystem (MMS) that would satisfy their requirements. This MMS should be configurable to suit a number of markets and applications as the requirements for different products and markets vary. For example, the memory requirements for all mobile phones can be grouped into one MMS, but configuration would differ between feature phones and smart phones, as the latter has more demanding applications such as video and Internet.

The ability to configure is significant since memory types, size and speed vary for different applications. Configurability enables the designer to adapt the system to the application.
Unfortunately, in many applications, behavioural information is insufficient. In these cases, the configurable memory subsystem is very forgiving and will allow it to be tuned to the application to better satisfy the system requirements.

Providing multiple memory types in one package simplifies system design and improves time-to-market

A single MMS should be lower cost and smaller due to a reduction in the number of chips, more effective layout and fewer pins. It should consume less power as all memories are considered in the design together and can share required resources. It should also provide higher performance when configurability is used for tuning the design to the application.

Additionally, a single interface to the MMS will reduce the design complexity of dealing with multiple interfaces as the MMS handles the complexity on behalf of the embedded system. Therefore, memory subsystem design is reduced to selecting the most fitting memory package and dealing with a single interface meaning a lower cost product and faster time to market.

Siamak Arya is senior director, system architecture, at Silicon Storage Technology.