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Saturday 22 November 2008
Design
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|NewsletterEDA and IP
ARM adopts boundary scan from XJTAG
Wednesday 5 September 2007
ARM has selected XJTAG’s boundary scan development system for debugging and testing its range of ARM RealView development hardware tools.
The microprocessor firm is using the boundary scan system on its RealView platform baseboards, which contain multiple high pin-count ball grid array devices.
“With tens of thousands of pins on each board, we recognised it would not be possible to validate these circuits in a commercially realistic timescale without a boundary scan test system,” said Spencer Saunders, engineering manager for system design at ARM.
Combining the boundary scan description language files for JTAG-compliant components with test scripts written for each device and the board netlist itself, the XJTAG boundary scan system will calculate how to manipulate the JTAG chain in order to access as many nets as possible, including those with non-JTAG devices. Board design changes are accommodated by recompiling using the revised netlist.
The microprocessor firm is using the boundary scan system on its RealView platform baseboards, which contain multiple high pin-count ball grid array devices.
“With tens of thousands of pins on each board, we recognised it would not be possible to validate these circuits in a commercially realistic timescale without a boundary scan test system,” said Spencer Saunders, engineering manager for system design at ARM.
Combining the boundary scan description language files for JTAG-compliant components with test scripts written for each device and the board netlist itself, the XJTAG boundary scan system will calculate how to manipulate the JTAG chain in order to access as many nets as possible, including those with non-JTAG devices. Board design changes are accommodated by recompiling using the revised netlist.
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