Freescale Semiconductor is to jump directly to a 45nm process for its embedded multicore Power Architecture devices shipping next year, reducing the size and power consumption of the chips by half compared to today's 90nm process.

A four core chip and an eight core device will be built on a 45nm silicon on insulator copper process by IBM and Chartered Semiconductor, initially for 3G and WiMax basestations.

"This new multi-core communications platform will be designed for 45nm silicon-on-insulator technology, skipping a whole generation of process technology and delivering power reduction and integration advantages that will advance the state of embedded computing," said Michel Meyer, chief executive of Freescale at last week's Freescale Technology forum in Paris.

The chips use a new interconnect fabric called CoreNet that will support more than 32 1.8GHz e500 Power processors on a core, as well as having the capability to add StarCore digital signal processor cores, expected in 2009. This fabric allows each core to have its own level 1 and level 2 cache, but still be fully synchronised with each other and with a shared level 3 cache on the chip.

The chips also have separate dedicated engines for security, packet processing and resource management that also link to the fabric.

"We have also incorporated our on-demand application acceleration technology, which is a collection of on-chip IP that helps to quickly secure and route traffic," he said. "This enables a network-based anti-virus solution that not only scans network traffic at the line rate but also mitigates active viruses and virus outbreaks."

Freescale has been working closely with high level simulation company Virtutech to develop models of the chips so that software developers can start working now before the chips are ready. The simulation environment allows high speed functional simulation but also links to a slower, cycle accurate simulator for debugging the code.

Freescale is planning a dedicated SERDES high speed serial interface specifically for debugging the chip rather than using the networking interface.