Memory firm Rambus is developing a 1Tbyte/s data bus for graphics processors and CPUs.

“It is not just frequency scaling in processors, but multi-core processors and multi-threading that is driving the demand for memory bandwidth,” v-p of engineering at Rambus Kevin Donnelly told EW. “A 1Tbyte/s system level configuration will have 16 DRAM elements, each 32 links wide, each running at 16Gbit/s.”

Getting a 16Gbit/s individual link working is the key to the whole scheme.

Existing double data rate (DDR) DRAM clocks data on both edges of an x86 processor’s system clock.

Rambus already has XDR, a scheme that clocks eight data bits every complete clock cycle.

The Terabyte Bandwidth Initiative, as the new development is known, will clock 32 data bits per clock cycle - hitting 16Gbit/s with a 500MHz clock.

All 16 data bits to each DRAM will be clocked by a single 500MHz clock, moving 512Gbit - 64Gbyte - per second to each memory chip.

The clock and data signals are all carried on differential pairs, with skew errors calibrated out by a training pattern during each DRAM refresh cycle, Rambus technical director Steve Woo told Electronics Weekly.

Why didn’t the firm switch to self-clocking data? “We have done a lot of systems with self timing, but the encode and decode adds to latency which is a big issue in memory systems,” said Donnelly.

For the first time, Rambus will move away from a parallel control/address (C/A) bus, instead introducing a serial address bus, ‘FlexLink’, which uses the same clock as the data and operates at the same 16Gbit/s.

How many of these C/A busses there are will depend on the applications.

Maximum PCB track length will be in the region of 150 to 200mm.

The firm will demonstrate Terabyte Bandwidth Initiative silicon operating at 16Gbit/s this week at its developers forum in Tokyo.