Intel will take the wraps off its quad-core Itanium, the first processor to exceed two billion transistors, at the International Solid-State Circuits Conference (ISSCC), to be held on February 3-7 in San Francisco.

It implements soft-error-immune storage elements in 99 per cent of its system-interface latches to counter high energy particle strike. It will also reveal details of its stripped down 2W 2GHz x86 processor which uses building blocks for more than one task as well as substantially disabling un-used logic to save power.

Among other significant announcements at ISSCC, Sun Microsystems is to describe a processor with a novel micro-architecture designed to support the formerly conflicting needs of single and multi-thread hardware. It has an instruction cache that is shared across four pipelines, and a data cache and floating-point unit that are shared across two pipelines, resulting in a hierarchy of 16 micro-cores organised as four core clusters, supporting 32 threads.

Amongst medical presentations, the University of Ulm will discuss its second-generation of imager chip to be implanted beneath the retina. With partners, the University is preparing a power system which will feed the implant through a ribbon wire from the eye under the skin to behind the ear.

Power will be wirelessly supplied, as is presently done with cochlear implants. Every pixel in the sensor array contains a photo-sensor, some logic, and an output driver.

The UK's Toumaz Technology will describe a wireless medical patch, including battery, that senses glucose/pH, motion, heart rate, temperature, and pressure. In an example of extreme analogue speed, researchers from Nortel and STMicroelectronics will demonstrate a 24GHz six bit successive approximation (SAR) ADC. Time interleaving 160 SAR converters allows the speed to be hit using only 1.2W in 90nm CMOS.

This is just a small sample of the circuits under discussion during ISSC this year.