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Saturday 10 January 2009
Design
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Move to 32nm could force design change for chips
Wednesday 19 March 2008
The move to 32nm semiconductor process technology could see a change in the way chips are designed, according to UK-based EDA tool supplier, Pulsic.
“For the wider market the technology could go one of two ways,” said Mark Waller, v-p of R&D at Bristol-based Pulsic.
There is the reduced design rules approach where the rules for all the tracks, vias and corners are the same, which is favoured by the traditional grid-based approach, or the shape based which can handle the real design rules that the process technology needs, according to Waller.
“We have proved it’s very easy for us to keep up with the rule changes because we look at the design rules for real rather than having a data abstraction,” he said.
This is increasingly important with 32nm technology. “People are gearing up for 32nm and starting to need use to cope with design rules at 32nm,” said Waller. “What our memory customers in the US, Korea and Japan are seeing is more refinement of the 45nm design rules and they need to be able to do custom design to get the smallest die area rather than have one reduced set of design rules.”
Pulsic launched a new version of its shape-based Unity design tool at the DATE conference last week, intended to be the upgrade for its original Lyric shape-based routing tool that is used by 9 out of the top 10 memory chip makers. Unity adds hierarchical floorplanning and is the way to get into other custom designs such as FPGA chip design, imaging chips, advanced analogue, LCD drivers and even LCD panels. As a result the company is also adding static timing analysis to the toolset for the wider market.
“Memory was the beachhead and a lot of what we do is driven by their needs, but we are moving on from that,” said Waller.
“For the wider market the technology could go one of two ways,” said Mark Waller, v-p of R&D at Bristol-based Pulsic.
There is the reduced design rules approach where the rules for all the tracks, vias and corners are the same, which is favoured by the traditional grid-based approach, or the shape based which can handle the real design rules that the process technology needs, according to Waller.
“We have proved it’s very easy for us to keep up with the rule changes because we look at the design rules for real rather than having a data abstraction,” he said.
This is increasingly important with 32nm technology. “People are gearing up for 32nm and starting to need use to cope with design rules at 32nm,” said Waller. “What our memory customers in the US, Korea and Japan are seeing is more refinement of the 45nm design rules and they need to be able to do custom design to get the smallest die area rather than have one reduced set of design rules.”
Pulsic launched a new version of its shape-based Unity design tool at the DATE conference last week, intended to be the upgrade for its original Lyric shape-based routing tool that is used by 9 out of the top 10 memory chip makers. Unity adds hierarchical floorplanning and is the way to get into other custom designs such as FPGA chip design, imaging chips, advanced analogue, LCD drivers and even LCD panels. As a result the company is also adding static timing analysis to the toolset for the wider market.
“Memory was the beachhead and a lot of what we do is driven by their needs, but we are moving on from that,” said Waller.
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