TSMC has said first wafers from its 40nm semiconductor manufacturing process are expected in the next three months. The foundry is claiming a x2.35 increase in gate density over the 65nm process, active power down-scaling of up to 15% over 45nm.

The 40nm process employs a combination of 193nm immersion photolithography and extreme low-k (ELK) material. The logic family includes a low-power triple gate oxide (LPG) option to support high performance wireless and portable applications. 

Both the G and the LP processes offer multiple Vt core devices and 1.8V, 2.5V I/O options to meet different product requirements.

Following tapeouts of its 45nm process technology in 2007, TSMC developed an enhanced 40LP and 40G process for the 40nm node.

“Our design flow can take designs started at 45nm and target it toward the advantages of 40nm,” said John Wei, senior director of advanced technology marketing at TSMC.

TSMC has developed the 40LP for leakage-sensitive applications such as wireless and portable devices and its 40G variant targeting performance applications including CPU, GPU, game console, networking and FPGA designs and other high-performance consumer devices. 

The 40nm footprint is linearly shrunk and the SRAM performance is fully maintained when compared to its 45nm counterpart, its SRAM cell size is now the smallest in the industry at 0.242µm sq.