The Return of the ASIC was predicted by the CEO of eASIC, Ronnie Vashista at the Globalpress Summit Conference in San Francisco yesterday.

ASIC and ASSP deign starts have been declining significantly to the point where, if the trends persist, there will be only 250 ASIC design starts in 2030. The reason is escalating cost and risk, $50m cost of a chip and a high chance of a re-spin.

That's all going to change. "I believe we are at an inflexion point where we're seeing a resurgence of ASIC back into the mainstream", said Vashista.

His means for getting there is customising an entire chip by using direct write e-beam on one Via.

"We have developed a proprietary architecture where a single via can be customised by direct-write e-beam", said Vashista. The patterning is done at eASIC's foundry, Fujitsu.

eASIC's approach has been tried before, notably by Lasarray and ES2. Asked why eASIC would be any more successful than those companies, Vashista replied:

"Those companies brought in their technologies when the alternative wasn't broken enough. Now we're seeing the decline aggressively happening."

He's bullish. "We're seeing the return of the ASIC in a disruptive form", he said, "we're bringing unique silicon back to the masses."