As CMOS process technology reduces well below 100nm, large numbers of gates can be had at relatively low prices. But the same is not true of mask sets, and the breakeven volume for application specific products – whether standard or custom – is increasing.

At the same time, designers need flexibility as typical lifetimes for end-user products become shorter and standards and protocols change quickly.

Given these conditions it is no surprise that reconfigurable devices such as FPGAs are winning sockets at an increasing rate. And, as vendors offer multiple variants within a single device family, emphasising capabilities such as DSP or I/O or general-purpose logic, orders over one million pieces are becoming increasingly commonplace. 

Product designers are using these devices to deal with pressure on cost/performance, short development cycles, and frequent updating of products in all but the highest volume opportunities.

In markets for video technology, for example, insatiable demand for high definition (HD) has taken off even while standards continue to evolve quickly. The availability of programmable devices with gigabit I/O capabilities and embedded processing eliminates the risk for equipment vendors that emerging standards will quickly outdate new products.

An example can be seen in the progression of HD transport protocols based on the SDI standards. The dominant 270Mbit/s SDI for uncompressed standard-definition video transport is giving way to next generation HD-SDI specifying a nominal data rate of 1.5Gbit/s. However, even faster standards are already emerging, including Dual-Link HD-SDI, which combines two HD-SDI links to support 3Gbit/s total bandwidth, and 3G-SDI achieving the same bandwidth over a single co-axial link.

The next step for HD studio equipment is to transmit HD streams over Ethernet (see diagram). This brings pre- and post-processing challenges to meet image-quality and latency requirements when transmitting multiple channels at high-definition resolution and full frame rate.

The Ethernet environment also demands flexibility to support a multiplicity of codecs. It will be tough for standard-IC vendors to commit to developing a solution in silicon. FPGAs, which can implement a combination of standard and proprietary IP including video cores and processing algorithms, are becoming recognised as providing the fastest route to leading-edge broadcast video performance.

In wireless communications, pressure from 3G operators to reduce cost-per-channel for infrastructure elements like basestations is driving developers toward a unified hardware platform that can be quickly and cost-effectively tailored to comply with differing cellular standards in territories worldwide.

Initiatives such as CPRI and OBSAI have emerged to open up the base station architecture, with the objective of supporting the modularity necessary for vendors to reduce cost and delivery time and enable MNOs to save network planning, build-out and maintenance. However, flexibility is essential as 3G network standards continue to evolve to support forthcoming network upgrades such as OFDM modulation, HSUPA and the arrival of 4G services based on 3G long term evolution (LTE) and WiMAX technology.

Basestation architectures are migrating towards programmable technology to reduce cost and risk, gain flexibility, and alleviate time-to-market pressures. Functional blocks such as embedded DSP multipliers, configurable block memory and high speed serial I/O in high-end FPGAs allow designers to solve key challenges such as forward error correction (FEC) and radio functions such as digital up/down conversion. Importantly, there is also the flexibility to change algorithms in the future and distribute upgrades to equipment in the field via the network.

In other markets, such as those for industrial networking equipment, designers’ objectives are highly application specific. There is intense interest in real-time, multi-mega­pixel machine vision, for example, to increase automation and drive up productivity. But frame rates exceed traditional software-based image-processing capabilities.

Standard video ICs, on the other hand, are driven by consumer market requirements, and are not designed around the functional requirements for ISM products. In any case, consumer ICs tend to have much shorter lifecycles than is required in the industrial space, and therefore impose long-term availability and support challenges.

To meet these demands and use the most advanced standard protocols as well as custom peripherals, designers are taking advantage of embedded signal- and control-plane processing resources as well as high-speed I/Os. Multiple parallel DSP multiply-accumulate blocks in the FPGA fabric accelerate processing for advanced digital vision applications.

With the accelerating trend toward greater functionality, improved power efficiency, shorter design cycles and reduced costs in embedded design, developers are increasingly seeking hardware-based solutions that are highly customised and efficient. While shrinking fabrication processes deliver CMOS gates at unprecedented low costs as well as low power consumption, reconfigurability is the key to accessing these benefits in practical designs.

Paul Evans is marketing manager at Xilinx