A key part of any analogue design flow is having models of the components for simulation. Traditional Spice models of basic components such as transistors and capacitors written in C or C++ are becoming increasingly complex, and so are the designs being simulated.

This combination means that simulating analogue designs accurately is taking longer and longer.

The problem for model developers is that the complexity in model development has shifted from creating the models to using them in the designs and simulations, and this is leading to fewer models being implemented. These models are also becoming more general to try to handle all different manufacturing processes.

At the same time, simulator model interfaces are becoming increasingly powerful, and as a result, increasingly complex. This makes the software engineering aspects of implementing the models very time-consuming, detracting from the job of designing analogue circuits.

There is also the problem that existing source-code interfaces are inherently non-portable; this requires close cooperation with the simulator vendor to make sure the model runs accurately.

Meeting user requirements
The challenges for the user are slightly different. They want accurate, robust, tried and tested models that can be used across different simulation tools and where the underlying equations can be easily modified to suit their particular needs.

These needs are met with the Verilog-A language, which provides a way of specifying a model in a standard way similar to the Verilog and VDHL hardware description languages.

This can now be used to write models of components either at the transistor and capacitor level such as bipolar junction transistors and Mosfets, or more complex circuits such as phase locked loops or oscillators. The technology has been proven to the point of providing the same accuracy as hand-crafted equations with more ease of use by non-specialist engineers.

A number of EDA vendors have integrated the compiler and simulator-specific run-time environment from Tiburon Design Automation into their tool flow.

Having a reliable, fast Verilog compiler for analogue then opens up the potential for top-down design for analogue systems, and integration with existing design flows. This allows the engineer to model the design at a high level using behavioural models written in Verilog-A.

Rather than being detailed models of the transistor level components, these models describe the behaviour of the blocks, often through equations. These are fast to develop and run, and give the designer a good idea of what the system will do at a very early stage. This opens up the possibilities of architectural exploration in the analogue design space for engineers who are not specialists in the technology, and allows the analogue elements of a design to be modelled at the same time as the digital elements in a consistent design flow.

Unfortunately there is no equivalent of digital synthesis for the analogue world, so these behavioural models need to be used as the detailed specification for the analogue blocks. These would then be developed using a schematic tool. 

The next steps are to combine the Verilog-A tool with the schematic editor so that the two are closely linked. This will allow the designer to highlight part of the Verilog-A and see the corresponding part of the schematic design and vice versa.

Faster simulation
Verilog-A has the capability to support complex compact model implementations for faster simulation of low level designs. Using Verilog-A allows designers who are not experts in C model development to easily write and modify the Verilog-A models for their exact needs, making the simulation process faster and more accurate. Most of the popular compact models have been implemented as a demonstration that designers can use as a template or modify for their own needs.

At the same time, using the right Verilog-A compiler provides fast execution and support for all analysis types to speed up the simulation further and allow top-level design in analogue systems.

This means model implementation and distribution can be greatly simplified to benefit end users, model developers and simulation vendors. Designers also benefit by the possibility of high-level architectural exploration in the analogue space, making designs more efficient in area and space, more reliable and better yields, all in a shorter design time with better verification.

Jeff Miller works for Tanner EDA