As the wireless industry transitions from a high-growth phase to a more mature state, so costs have risen across the entire wireless infrastructure, including the base­station. Next-generation basestation deployments must continually reduce cost (as measured by cost per channel) but also add functionality to support new services, protocols and changing subscriber usage patterns.

The complexity required of a base­station has increased by an order of magnitude, while the selling price of a typical basestation has fallen from over $100,000 to less than $20,000 in a decade. Manufacturers are responding to this dilemma by design ing and maintaining a common architecture that lets them slim down their manufacturing, design and support requirements and focus instead on the software and programmable hardware that provides the extra functionality.

For operators, lower basestation costs and greater commonality helps with network planning, build-out and maintenance, and cuts start-up and expansion costs.

Wireless basestation designs have shifted from application-specific integrated circuits (Asics) towards off-the-shelf components, such as digital signal processors (DSPs) and field programmable gate arrays (FPGAs). This shift is driven by declining unit volumes and an increase in processing power, which enables a much lower cost per channel.

Most development today is based on a mixed architecture of DSPs, FPGAs and Asics, although the num­ber of Asic designs has fallen in many OEMs after early-3G systems failed to take off. When the operators were ready, they wanted the next revision of the standard, which the Asic was not designed to meet.

Wimax and 3GPP
Arrays of DSPs, or DSP chips with multiple processing units, can primarily be found performing baseband processing in the basestation. But designers are finding it increasingly difficult to meet the low-latency performance requirements of the latest Wimax and 3GPP long-term evolution (LTE) standards.

Programmable hardware, in the form of FPGAs, allows critical high-performance baseband functions such as Turbo Decoding to be off­loaded, freeing up processor cycles and improving data throughput.

FPGAs can be found throughout the basestation, linking the subsystems, and providing the necessary performance in critical sections. This is especially true of the RF transceiver cards, where the amount of digital processing is rising as OEMs strive to reduce costs by trading more complex digital signal processing for large cost savings and better power amplifier efficiency.

Much has also been written about software-defined radio, which is seen as the ultimate goal of a common platform. In a software-defined radio, everything is programmable and the system can handle all wireless standards seamlessly simply through reprogramming.

While a true software-defined radio system has not yet reached the cost goals required for deployment in commercial equipment, great strides have been made by suppliers looking to support the US military communications initiative, the Joint Tactical Radio System (JTRS). Delivery has started on JTRS-compatible radios, showing that programmable, high-quality, extremely reliable systems can be built with a software-defined radio approach. It is only a matter of time before the same will be possible in the commercial cellular market.

David Nicklin works in the wireless team at Xilinx