Collaborating with Hitachi, researchers at the University of Surrey have created Fets in amorphous silicon with improved leakage and speed using thin channels. Circuits deposited on glass could benefit.

Normally, grain boundaries and other defects in amorphous silicon reduce the mobility of wanted carriers, while creating random carriers - resulting in sluggish leaky transistors.

The transistor has a channel far thinner than conventional amorphous transistor channels - only 2nm thick - and made in amorphous silicon so fine it has been dubbed nanocrystaline.

"With thin channels, the quantum confinement effect dominates and the bandgap of the material becomes wide so leakage current decreases," researcher Dr Xiaojun Guo told Electronics Weekly.

'On' current also decreases, but at a lower rate. "The decrease in on current is much smaller than the decrease in off current," said Guo.

With a 2.5V gate voltage swing, the on/off ratio of the Hitachi/Surrey transistors is 10[super11] - a value which, according to the university, is impossible to achieve with conventional transistors in disordered silicon.

To make the thin channel, it has to be formed in nano crystalline amorphous silicon - Surrey has measured its crystals at 10nm across. "10nm grains are not difficult," said Guo. "We use a very slow rate of chemical vapour deposition."

The devices were firstly fabricated by Hitachi and used for low power memory design. "We built collaborations with Hitachi after that, and focus on the characterisation and modelling of the devices, and the idea of using the technique to design high on-off ratio transistors for large area electronics," said Guo, of Surrey's Advanced Technology Institute (ATI).

Initial devices were deposited on 200mm silicon wafers and Guo sees no problems in making them on glass as deposition temperatures are low.

Plastic is another possibility, although internal stress will break the nanocrystal layer in places. "If we can deal with stress sufficiently, say with a buffer layer, we could have something."

Surrey's ATI has a second device that circumvents the shortcomings of deposited silicon: the source-gated transistor proposed by Professor John Shannon.

"Compared to a field-effect transistor, the SGTs can operate with very short source-drain separations even with a thick gate insulator layer to achieve high speed, good stability and superior control of current uniformity, providing a significant advantage in terms of the fabrication process," said the University.

With two alternative ways to improve amorphous silicon circuit performance, ATI director Professor Ravi Silva thinks consumers will benef: "This work will help extend the already well established CMOS fabrication technologies for use in large area applications such as displays and sensors, which are at the heart of consumer electronics," he said. "The ATI is fortunate that we have been at the forefront of two potential technologies that can lead to enhanced device performance in disordered materials by clever nano-scale structural design of disordered transistors."

Both projects are part-sponsored by the Engineering and Physical Sciences Research Council (EPSRC).