To support verification interoperability standardization in the semiconductor design industry, Mountain View, Calif.-based semiconductor design and manufacturing software supplier Synopsys Inc today reported that it is donating its complete implementation of the Verification Methodology Manual (VMM) verification methodology for SystemVerilog, including the VMM Standard Library and VMM Applications, to standards organization Accellera.

As such, Accellera has accepted the donation so its recently formed verification IP (VIP) technical subcommittee can use it for standardization activities.

The VMM methodology was originally defined in the Verification Methodology Manual for SystemVerilog and has been by hundreds of verification teams since its introduction in 2005, Synopsys reminded.

This donation is meant to address customer demands for a modular, scalable and reusable design methodology standard while allowing for easier development and the ability to share complex verification environments, the company also said.

“Accellera’s newest standardization activity will promote interoperability among vendors’ and users’ verification methodologies. The donation of Synopsys’ VMM implementation provides the technical subcommittee with established technology to meet their objectives,” said Shrenik Mehta, Accellera chair, in a statement.

Synopsys has donated its complete implementation of the VMM methodology, which includes:

• VMM Standard Library
  
• VMM Register Abstraction Layer application
  
• VMM Reusable Environment Composition application
  
• VMM Memory Allocation Manager application
  
• VMM Hardware Abstraction Layer application
  
• VMM Data Stream Scoreboard application
  
• VMM Macro Library