Richard Rice, Oconomowoc, WI; Edited by Charles H Small and Fran Granville - EDN, 15/5/2008

Overlap—the short period during which a push-pull drive’s two transistors are both simultaneously on—is a common problem with these drives in a center-tapped transformer’s primary. Overlap causes a large current spike and increased switching losses. The fact that saturated transistors turn off more slowly than they turn on causes the problem. One method of preventing overlap is to provide a time delay after turning off one transistor and before turning on the other one.

This method requires several extra components and must include enough delay for a worst-case scenario. This Design Idea uses cross-coupled gates to prevent one transistor from turning on before the other turns off (Figure 1). For simplicity, the figure omits the depiction of bypass capacitors, snubber networks, and other components unnecessary for illustrating the method.

Gate IC2A prevents Q1 from turning on until Q2 turns off. Likewise, gate IC2C prevents Q2 from turning on until Q1 turns off. Gates IC2B and IC2D function as inverters to provide the correct polarity to drive the switching transistors. Monitoring the transistors’ collector voltages senses the turn-off of each transistor using the voltage dividers R3/R4 and R5/R6.

Because the collector voltage swings to twice the supply voltage, the voltage dividers halve the voltage. The impedance of the voltage dividers also limits the gates’ input current to a safe level during overshoot. The switching frequency is one-half the input-clock frequency. D-type flip-flop IC1A divides the input-clock frequency by two and provides complementary outputs with a 50% duty cycle. The complementary outputs drive the switching transistors in an alternating sequence. The secondary of transformer T1 provides an isolated square-wave output.