Altera has unveiled plans for Stratix IV, its 40nm FPGA family, which comes with a matching Asic family dubbed HardCopy IV.

Made by TSMC using 193nm immersion lithography, strained silicon, and low-k dielectrics, Stratix IV devices have up to 680,000 logic elements (LEs), twice that of the largest Stratix III device.

Within the family are 'GX' chips with 8.5Gbit/s transceivers - up to 48, and 'E' FPGAs with no transceivers.

GX devices also include hard wired support for PCI Express Gen 1 and Gen2, Serial RapidIO, XAUI, CPRI, CEI 6G, Interlaken and Ethernet. Up to four x8 mode PCIe cores are provided.

In addition to the number of logic elements, headline figures include 22.4Mbit of internal RAM, and 1,360 18x18 multipliers "probably worth as many gates as the random logic in total," said Altera marketing director Paul Hollingworth of Altera, as well as 350MHz operation from the 0.9V core logic.

Per function power consumption is halved compared with the firm's previous FPGAs. "People would always ask for more performance, until we hit 90nm when power became the issue," said Hollingworth. "From Stratix III to IV the power envelope has not increased - you get twice the logic elements for the same power."

GX devices range from eight to 48 transceivers and 70,000 to 530,000 LEs. E devices have between 110,000 and 680,000 LEs.

In a design example, Altera proposes that - with added RAM and analogue components - a complete WCDMA plus wireless broadband femtocell would fit into its 360,000 LE Stratix IV running at 200MHz and dissipating 4W.

Altera introduces its HardCopy Asics for firms needing to reduce costs at high volumes or save power, said Hollingworth, and 160 conversions have been made since 2002. "Nine out of our 10 top customers have used HardCopy," he said.

For the first time, Altera has put transceivers onto its HardCopy ASICs - using the same block as the FPGAs.

Successful transition from Stratix to HardCopy is guaranteed, said Hollingworth, providing the appropriate switch is thrown in the associated Quartus II EDA tool when the FPGA is first designed.

Currently there are no completed Stratix IV devices. Instead TSMC has finished two test chips that are now with Altera: One with multiple 8.5GHz transceivers that Hollingworth claims is actually operating at 10GHz in the lab, and the other is a copy of an existing 500 million transistor Stratix III device.

The Stratix/HardCopy IV iteration of Quartus II (v8.0) is due out on June 2nd, followed by a 230,000 LE FPGA with transceivers in the last quarter of this year. "This will be closely followed by a 530,000 GX," said Hollingworth, "and HardCopy will be about a year later."

HardCopy III devices will also be made on the 40nm TSMC process. "We decided not to make a big song and dance about HardCopy III. It is a different die on the same platform," said Hollingworth.