California start-up SiliconBlue has revealed details of its low power SRAM FPGAs for handhelds, with on-chip non-volatile memory.

The aim, said the company, is to offer Asic-like logic capacity for battery-powered, handheld consumer applications.

The devices are based around the traditional four-input look-up table (LUT) logic cell. "Essentially, it is a 16-bit RAM with a register on its output which can be bypassed," v-p strategic marketing John Birkner told EW.

Power savings come from selecting the low power transistor option of TSMC's standard 65nm CMOS process, which includes low k dielectrics.

The first product, iCE65L04, is sampling now and has 4,000 logic cells. Its core consumes under 25[micro]A running at 32.768kHz, and benchmarking at 32MHz, a full load of 16bit counters consumes 7-9mA, said Birkner.

In selecting TSMC's low power option, SiliconBlue has constrained itself to a maximum operating frequency of 200MHz.

"Processes are overkill on performance, so we thought back and applied power savings," said Birkner, pointing out that mobile DDR runs at 133MHz.

Although the device can be booted from an external memory or microcontroller, it also includes a once-programmable non-volatile configuration memory for use if field modifications are not required. "It's based on TSMC's oxide disruption and only occupies two per cent of the die," said Birkner.

The family, which will eventually have four members with from 2k to 16k logic cells, 128 to 384 I/O pins and in packages from 3x4 to 12x12mm, is aimed at applications including power saving co-processors - including MP3 and JPEG decode, human interface controllers, and glue logic.