Paving the way for green data centres, researchers in IBM's Zurich, Switzerland labs have demonstrated a prototype that integrates a cooling system into 3D chips that pipes water directly between each layer of stacked circuits and components.

The prototype design was created in collaboration with the Fraunhofer Institute in Berlin that IBM said promises to advance Moore's Law in the next decade and significantly reduce energy consumed by data centres.

The 3D chip stacks take chips and memory devices that traditionally sit side-by-side on a silicon wafer and stacks them together on top of one another and has presented what IBM also said is one of the most promising approaches to enhancing chip performance beyond its predicted limits.

This follows IBM's chip-stacking technology announcement last April that it said would ready the path for 3D chips containing "through-silicon vias," to allow different chip components to be packaged closer together for faster, smaller and lower-power systems. The technology shortens the distance that information on a chip needs to travel by 1000 times, and allows for the addition of up to 100 times more channels, or pathways, for that information to flow compared to 2-D chips.

"As we package chips on top of each other to significantly speed a processor's capability to process data, we have found that conventional coolers attached to the back of a chip don't scale. In order to exploit the potential of high-performance 3D chip stacking, we need interlayer cooling. Until now, nobody has demonstrated viable solutions to this problem," explained Thomas Brunschwiler, project leader at IBM's Zurich Research Laboratory, in a statement.

IBM estimated that 3D chip stacks would have an aggregated heat dissipation of close to 1 kilowatt, which is 10 times greater than the heat generated by a hotplate, with an area of 4 square centimeters and a thickness of about 1 millimeter. In addition, each layer poses an additional barrier to heat removal.

Brunschwiler said he and his team piped water into cooling structures as thin as a human hair (50 microns) between the individual chip layers in order to remove heat efficiently at the source, and by using the thermophysical qualities of water, scientists were able to demonstrate a cooling performance of up to 180 W/cm2 per layer for a stack with a typical footprint of 4 cm2.

Bruno Michel, manager of the chip cooling research efforts at the IBM Zurich Lab said this development constitutes a breakthrough particularly since the stacking of two or more high-power density logic layers is impossible with classic backside cooling.

Specifically, scientists piped water through a 1 by 1 cm test vehicle, consisting of a cooling layer between two dies or heat sources with the cooling layer measuring only about 100 microns in height and packed with 10,000 vertical interconnects per square centimetre.

The researchers said they overcame key technical challenges in designing a system that maximizes the water flow through the layers, yet hermetically seals the interconnects to prevent water from causing electrical shorts, with the complexity of the system resembling a human brain, wherein millions of nerves and neurons for signal transmissions are intermixed but do not interfere with tens of thousands of blood vessels for cooling and energy supply, all within the same volume.

The fabrication of the individual layers was accomplished with existing fabrication methods, except those needed to etch or drill the holes for signal transmission from one layer to the next, IBM explained. To insulate the "nerves," scientists left a silicon wall around each interconnect (through-silicon vias) and added a fine layer of silicon oxide to insulate the electrical interconnects from the water. Then, the structures had to be fabricated to an accuracy of 10 microns, 10 times more accurate than for interconnects and metallizations in current chips.

To assemble the individual layers, Brunschwiler and his team, along with colleagues from the Fraunhofer Institute developed a thin-film soldering technique which was used to achieve the high quality, precision and robustness needed to ensure excellent thermal contacts as well as electrical contacts without shorts.

In the final setup, the assembled stack was placed in a silicon cooling container resembling a miniature basin and water is pumped into the container from one side and flows between the individual chip layers before exiting at the other side.

Using simulations, scientists extrapolated the experimental results of their test vehicle to a 4-square-centimeter chip stack and achieved a cooling performance of 180 W/cm2.

Brunschwiler noted that he and his team are working to optimise cooling systems for even smaller chip dimensions and more interconnects, as well as investigating additional sophisticated structures for hotspot cooling.

By Ann Steffora Mutschler, Senior Editor - Electronic News