To achieve higher gate density and improved cost-performance in next-generation 45nm CMOS semiconductor manufacturing technology, Tokyo-based semiconductor company Toshiba has reported a new compact model for circuit design during a session at the VLSI Symposium being held in Honolulu, Hawaii this week

Toshiba explained that by applying this technique, gate density for 45nm CMOS technology is boosted to 2.6 times higher than that of 65nm CMOS technology, and surpasses the typical gain of 2 times that is realized from generational migration.

Proximity effects in a circuit design layout are the leading factor in the variability of transistor performance, while gate density plays an important role in chip cost and by applying this technique to the design in 45nm CMOS technology, Toshiba said it achieves both high performance and cost competitiveness in system LSI.

Toshiba's technique predicts the performance of each transistor individually by focusing on factors dependent on circuit layout.

In 65nm CMOS technology, gate length, gate width and the distance between the gate and isolation area are considered to be as major factors affecting transistor performance, while in 45nm CMOS technology and beyond, additional factors such as the space of gates and locations of contacts are modelled and fed into the design.

Toshiba noted that its technique estimates each transistor characteristic and feeds them into the circuit design resulting in higher gate density without increasing the margin for variability in design.

While advances in process technology have required shorter gate lengths in CMOS process technology, and application of stress enhancement techniques has proved effective as a means to improve transistor performance, beginning at the 45nm CMOS process node, gate length scaling will advance significantly, and the application of stress enhancement techniques will produce complicated variability as a result of dependence on layout in the design, the company asserted.

In terms of stress enhancement techniques, Toshiba explained that increasing carrier mobility in CMOS transistor is an effective means to obtain better transistor performance, as it can be modulated by applying strain at transistors.

Toshiba's technique utilizes this phenomenon. Various techniques have been proposed for imposing stress at the transistor channel area including forming stress films over transistors, or embedding stress films on both sides of the transistor gates but these techniques create a complicated proximity effect dependant on actual transistor layout and causes concerns for increased variability in transistor performance.

Finally, the issues associated with stress enhancement could be avoided in earlier generations by setting an additional design margin for safer design or by restricting the pattern and design although this approach sacrifices improvement in gate density and is insufficient for the 45nm CMOS generation and beyond, Toshiba concluded.

By Ann Steffora Mutschler, Senior Editor - Electronic News