Wireless baseband processing is a demanding application, which requires a high-performance power-efficient solution. Any system must also be flexible, to accommodate the demands of multiple standards. This article examples various factors in the design process, including the choice of processor, interconnect and software platform.

Choosing the processor
The main choices for the processor are DSPs and FPGAs. In the past DSPs were the standard solution, but the main FPGA vendors have improved their signal processing offerings, and choosing the best solution can seem complex.

High performance DSPs offer ever-faster clock speeds and powerful multi-core solutions. Experienced developers have built up a wealth of field proven application code to run on the DSP cores. DSPs, though, are not well suited to parallel processing tasks: multiple devices can be required for tasks which take only a small proportion of the logic elements of an FPGA.

However, FPGAs are far from ideal for processing sequential conditional data flow. Also, the ever changing protocols of emerging standards make the DSP route attractive for some data processing: algorithms can be readily implemented in an accessible language such as C.

The flexibility of FPGAs has traditionally come with an additional cost in power due to the increased gate count and silicon area of non-optimised solutions in comparison to hard-wired architectures. However, 65nm technologies and the use of equivalent Asic technology for volume manufacture mean that FPGAs can be power-reduced.

If power consumption is considered on a per-channel basis, FPGAs can score better than DSPs, even though the chip-level power dissipation is higher. DSPs consume 3-4W typically and FPGAs 7-10W but can handle 10 times the channel density.

Some DSPs include power management to allow overall system power dissipation to be reduced during times of low traffic or to prevent over-temperature. Of course a suitable FPGA configuration could similarly manage its clock domains.

In recent years, there has been a trend towards FPGAs that incorporate DSP technology such as banks of embedded multipliers, for example Xilinx Virtex-4 FX devices. This enables the FPGA to incorporate DSP algorithmic processing for tasks which are not naturally parallel. Similarly, DSP vendors have introduced hardware co-processors to handle processing previously farmed out to an FPGA. For example TI’s TCI6482 DSP includes Viterbi and turbo decoders for 3GPP and 3GPP2.

There are other options beyond DSPs and FPGAs. Massively parallel processors are one alternative, but unfortunately often require the use of the vendor’s proprietary toolset. Asics and ASSPs are also well-suited to certain signal processing tasks, but their high up-front costs rule them out except in high volume applications.

Software issues for multi-processor systems
Handling multiple processors, which are often themselves multi-core, can be far from straightforward. Efficiently managing the processor cores, as well as shared resources such as memory and peripherals, means the per-channel cost and power dissipation can be minimised.

The increased number and complexity of processors required for wireless baseband applications has encouraged a move to third-party software platforms, which can cut time to market and development costs. For example, Enea’s dSPEED platform provides debug, management, and control capabilities needed to ensure continuous operation for data plane blades equipped with high-density DSP farms.
 
Interconnects
Choosing the best interconnect technology is obviously also important. A typical Wimax baseband system might have between 24-48 antenna streams per base station, with data rates upwards of 123Mbit/s per stream. This is an overall total of 3-6Gbit/s of antenna data.

When supporting multiple-input multiple-output (MIMO) systems with channels encoded using spread-spectrum techniques such as CDMA, data from all radio antennas has to be available to all baseband processing blocks. To achieve good performance, the key is an efficient low-latency interconnect.

A very popular choice in this kind of application is Serial RapidIO (SRIO), which is already implemented on the main DSP choices for baseband processing, and can be obtained with standard FPGA IP cores. It has a lower protocol overhead compared to Ethernet, and supports multiple masters, unlike PCI Express. SRIO’s multicast feature is also very important in distributed systems.

Let’s consider an example of a next-generation wireless baseband subsystem, designed to handle the higher data rates of Wimax and 3G. This could be built upon the AdvancedMC standard, and to get the required level of performance could include three high-performance DSPs, such as Texas Instruments’ TCI6487 or TCI6488, along with an FPGA.

In operation, the radio data is linked to the card via an industry standard CPRI or OBSAI interface. One DSP could be used for each Wimax sector, or the DSP loading could be fully flexible. An FPGA is used as a co-processor to handle OFDMA processing of the antenna data, and SRIO is used as an efficient interconnect to move data to and from multiple cards in a base station, and between processors on each card.

Using the AdvancedMC form factor enables a base station platform to be deployed based on a MicroTCA open standard chassis. Together with baseband processing boards, other essential elements (such as backhaul interfaces, network synchronisation and timing cards, and control processor AdvancedMCs) can be added “off the shelf” from a rich ecosystem of suppliers. A MicroTCA controller hub ensures the synchronisation of cards across the chassis and the distribution of radio data over SRIO and/or Ethernet.

Edward Young is managing director of CommAgility