Bread Crumb Menu
-
You are in:
- Home
- Design
- EDA and IP
Monday 1 December 2008
Design
Latest News
|NewsletterEDA and IP
Verilog-analog mixed-signal standard approved
Thursday 21 August 2008
The new standard is meant to unify Verilog HDL standard IEEE Std. 1364 with Accellera's AMS standard, to allow easier implementations by tool developers and more efficient top-down verification.
To allow the development of standard and tightly integrated Verilog-AMS modules and allow EDA software tool developers to implement EDA tools without ambiguities in the language interpretation, EDA standards organisation Accellera announced today that its board of directors and technical committee members including systems, semiconductor and design tool companies have approved a new version of its Verilog-analog mixed-signal (AMS) standard, Verilog-AMS 2.3, as an Accellera standard for analog and mixed-signal design and simulation.
The standard aims to unify the Verilog-AMS 2.2 specification with IEEE Std. 1364-2005 or Verilog hardware description language (HDL) standard.
Accellera said that Verilog-AMS 2.3 encompasses analog and mixed-signal extensions to IEEE Std. 1364, which is widely used today for digital circuit design and verification. The previous Accellera Verilog-AMS standard, Verilog-AMS 2.2, was approved in 2005.
“The Verilog-AMS 2.3 language release is an important milestone for our Technical Committee and the industry at large. A unified Verilog-AMS language integrated with the IEEE Verilog standard improves AMS design and will result in an increased acceptance of the standard,” said Shrenik Mehta, Accellera chairman, in a statement.
Specifically, Verilog-AMS 2.3 introduces new analog and mixed-signal features to support and enable improved top-down AMS design and verification methodologies, apart from IEEE-1364 integration including enhancements to table_model, support for multiple analog blocks, and resolution of language conflicts with the SystemVerilog IEEE Std. P1800, such as, changing the digital domain name to 'ddiscrete' from 'logic' as logic is a keyword in SystemVerilog, and making the usage of array literals consistent, Accellera said.
Accellera added that the next phase of AMS technical activities will include integration of the AMS standard with the SystemVerilog language, IEEE Std. P1800, and extensions to the AMS language for mixed-signal assertions and behavioral modeling support.
Ann Steffora Mutschler is senior editor with Electronic News
To allow the development of standard and tightly integrated Verilog-AMS modules and allow EDA software tool developers to implement EDA tools without ambiguities in the language interpretation, EDA standards organisation Accellera announced today that its board of directors and technical committee members including systems, semiconductor and design tool companies have approved a new version of its Verilog-analog mixed-signal (AMS) standard, Verilog-AMS 2.3, as an Accellera standard for analog and mixed-signal design and simulation.
The standard aims to unify the Verilog-AMS 2.2 specification with IEEE Std. 1364-2005 or Verilog hardware description language (HDL) standard.
Accellera said that Verilog-AMS 2.3 encompasses analog and mixed-signal extensions to IEEE Std. 1364, which is widely used today for digital circuit design and verification. The previous Accellera Verilog-AMS standard, Verilog-AMS 2.2, was approved in 2005.
“The Verilog-AMS 2.3 language release is an important milestone for our Technical Committee and the industry at large. A unified Verilog-AMS language integrated with the IEEE Verilog standard improves AMS design and will result in an increased acceptance of the standard,” said Shrenik Mehta, Accellera chairman, in a statement.
Specifically, Verilog-AMS 2.3 introduces new analog and mixed-signal features to support and enable improved top-down AMS design and verification methodologies, apart from IEEE-1364 integration including enhancements to table_model, support for multiple analog blocks, and resolution of language conflicts with the SystemVerilog IEEE Std. P1800, such as, changing the digital domain name to 'ddiscrete' from 'logic' as logic is a keyword in SystemVerilog, and making the usage of array literals consistent, Accellera said.
Accellera added that the next phase of AMS technical activities will include integration of the AMS standard with the SystemVerilog language, IEEE Std. P1800, and extensions to the AMS language for mixed-signal assertions and behavioral modeling support.
Ann Steffora Mutschler is senior editor with Electronic News
Site Navigation
Blogs on EW
Mannerisms
Chip industry musings from David Manners
Electro-RamblingsEW website blog, highlighting new content and features
Made by MonkeysAnalysis of bad designs
Gadget FreakBuild ingenious inventions, win £250
Parallel LinesNews and analysis on parallel processing
Directive DecoderGary Nevison on industry legislation
UK Tech StartupsNews on funding for electronics startups
Chips and BeerOut on the far flung semiconductor trail