There are many types of designs being put into FPGAs today, but one type of design stands out – image and signal processing algorithms – because of its significant role in providing product differentiation.

Algorithms are usually defined in an executable format. C or MATLAB are the two most common languages and many developers throw out the executable specification to rewrite the algorithm in RTL, which is really the wrong tool for the job. To dramatically simplify the path from image and signal processing algorithms to FPGA implementation, designers should choose an abstract language-based synthesis technology to use the executable specification as the starting point for implementation.

Algorithm capabilities
Algorithms represent a unique and high-value part of most systems. Algorithms are typically developed and validated at an abstract level using MATLAB or C. The process of manually converting these abstract models into RTL forces developers into an architecture immediately.

Making use of high-level synthesis tools gives the developer an environment to explore implementation options.

Time that can be saved by using the right tool for the job. The natural question is, what makes this possible? The answer is actually a number of capabilities that algorithm-level design allows, but in order to provide better guidance on evaluating algorithm to FPGA tools, there are three things that deliver the majority of the savings: faster verification, better partitioning and ease of adding parallelism.

Faster verification
Contrasting C with RTL for verification is easy, especially abstract C code. Abstraction equates to performance. C code that is synthesis-ready is less abstract than the original C code, but still more abstract than the original RTL that would be handwritten or generated by the C synthesis process. The impact is faster turn-around times and more confidence that changes and improvements have not compromised the functionality. If the tool also supports hardware-in-the-loop execution with the testbench, designers get even higher performance and confidence that the portion of the algorithm implemented in an FPGA works.

Partitioning and parallelism
Algorithm implementation is a balancing act of performance, cost and power trade-offs. Most often a combination of hardware and software is used to implement the algorithm. Using profiling on the abstract algorithm model gives immediate focus on the performance bottlenecks. This information, along with the developer’s experience, makes it easier to determine whether an FPGA can help break these bottlenecks.

Once identified, defining the interface for the portions of the algorithm that will run on the FPGA must be easy to handle in a good algorithm development environment. This is where using high-level synthesis to create all the necessary interface control logic delivers substantial time savings and correct-by-construction results over hand-developed interfaces and control.

The goal for moving an algorithm to an FPGA is to gain performance through parallelism. Again this is where developers will want a development tool to enable them to quickly direct the compiler to which functions/lines of code are to be executed sequentially and which can be run in parallel. The better the control provided the designer and the faster the turnaround time, the bigger the savings in development time and the higher the quality of results.

Larry Melling is v-p of marketing at Agility Design Solutions