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Friday 21 November 2008
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|NewsletterProgrammable Logic and Asic
Asynchronous FPGA clocks at 1.5GHz
by Steve Bush
Tuesday 16 September 2008
Californian start-up Achronix has revealed details of its 1.5GHz asynchronous FPGA, which includes 10.3Gbit/s serialiser/deserialisers (serdes).
“We get our speed from the underlying silicon technology,” said founder and CEO John Holt. “It represents a three-fold increase in performance over existing FPGAs.”
Realising that asynchronous operation has scared off customers in the past, the asynchronous core is wrapped in synchronous I/O and the company has opted for a well-known FPGA structure.
“The architecture is four-input look-up table [LUT], very much like the original Vertex and very much like the original Stratix,” said Holt. “Customers use standard RTL and industry synthesis tools.”
Back end processes including place and route are handled by in-house ‘ACE’ tools - for Achronix CAD Environment.
Although the product is an SRAM-based FPGA, the firm is not chasing traditional FPGA vendors. “Our business plan is not to take a single socket from Xilinx or Altera,” said Holt. Instead he is looking at higher throughput applications. “There are all these people out there who have to use standard cell and structured asics and would love to use an FPGA.”
Achronix first product, the 47,040 look-up table SPD60, has been shipping for a month and to underline his marketing point Holt revealed that the customer product expected to launch first uses four SPD60s and two Altera FPGAs.
Within Achronix FPGAs the repeating logic block has eight four-input look-up tables, storage elements and 128 bits of RAM. These logic blocks are surrounded by interconnect and asynchronous data routing blocks.
The asynchronous logic is differential return-to-zero, consisting of wire pairs with 01 and 10 indicating logic 0 and logic 1, or 00 indicating no data. A third wire sends back an acknowledge signal when data has been accepted from a pair.
This present-acknowledge structure inherently turns the data path into a pipeline - Achronix calls its architecture ‘microPipe’ - with valid data at all points in the pipe.
“With traditional globally-clocked FPGAs the clock rate must allow for the slowest path in the entire clock domain. Any combinatorial logic faster than the slowest path - all remaining logic - waits for the slowest one to finish,” said Holt. “Achronix technology allows fine-grained pipelining which allows more data values in flight which equates to faster throughput.”
Tools allow parallel pipeline lengths to be balanced and, knowing maximum asynchronous delays, calculate the fastest synchronous I/O clocking rate that guarantees valid data.
There are 20 10.3Gbit/s serdes on the SPD60, supporting 40G/100G Ethernet, CEI-6G, 10Gbit/s backplane, XFI, PCI Express (Gen 1 and 2), XAUI, Serial Rapid IO and Infiniband.
The chips also include a complete out-of-the-box DDR2/DDR3 interfaces including a physical layer and controller supporting memory interface speeds of up to 1.066Gbit/s.
Volume pricing for the 24,000 to 163,000 LUT family ranges from under $200 to $2,500.
“We get our speed from the underlying silicon technology,” said founder and CEO John Holt. “It represents a three-fold increase in performance over existing FPGAs.”
Realising that asynchronous operation has scared off customers in the past, the asynchronous core is wrapped in synchronous I/O and the company has opted for a well-known FPGA structure.
“The architecture is four-input look-up table [LUT], very much like the original Vertex and very much like the original Stratix,” said Holt. “Customers use standard RTL and industry synthesis tools.”
Back end processes including place and route are handled by in-house ‘ACE’ tools - for Achronix CAD Environment.
Although the product is an SRAM-based FPGA, the firm is not chasing traditional FPGA vendors. “Our business plan is not to take a single socket from Xilinx or Altera,” said Holt. Instead he is looking at higher throughput applications. “There are all these people out there who have to use standard cell and structured asics and would love to use an FPGA.”
Achronix first product, the 47,040 look-up table SPD60, has been shipping for a month and to underline his marketing point Holt revealed that the customer product expected to launch first uses four SPD60s and two Altera FPGAs.
Within Achronix FPGAs the repeating logic block has eight four-input look-up tables, storage elements and 128 bits of RAM. These logic blocks are surrounded by interconnect and asynchronous data routing blocks.
The asynchronous logic is differential return-to-zero, consisting of wire pairs with 01 and 10 indicating logic 0 and logic 1, or 00 indicating no data. A third wire sends back an acknowledge signal when data has been accepted from a pair.
This present-acknowledge structure inherently turns the data path into a pipeline - Achronix calls its architecture ‘microPipe’ - with valid data at all points in the pipe.
“With traditional globally-clocked FPGAs the clock rate must allow for the slowest path in the entire clock domain. Any combinatorial logic faster than the slowest path - all remaining logic - waits for the slowest one to finish,” said Holt. “Achronix technology allows fine-grained pipelining which allows more data values in flight which equates to faster throughput.”
Tools allow parallel pipeline lengths to be balanced and, knowing maximum asynchronous delays, calculate the fastest synchronous I/O clocking rate that guarantees valid data.
There are 20 10.3Gbit/s serdes on the SPD60, supporting 40G/100G Ethernet, CEI-6G, 10Gbit/s backplane, XFI, PCI Express (Gen 1 and 2), XAUI, Serial Rapid IO and Infiniband.
The chips also include a complete out-of-the-box DDR2/DDR3 interfaces including a physical layer and controller supporting memory interface speeds of up to 1.066Gbit/s.
Volume pricing for the 24,000 to 163,000 LUT family ranges from under $200 to $2,500.
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