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Friday 21 November 2008
Components
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|NewsletterProgrammable Logic and Asic
Xilinx targets 100Gbit Ethernet with Virtex-5 FPGA
by Steve Bush
Tuesday 23 September 2008
Xilinx has produced the TXT FPGA family aimed at 40 and 100Gigabit Ethernet.
Based on existing Virtex-5 intellectual property, the head of the family incorporates 48 6.5Gbit/s transceivers giving it 600Gbit/s bandwidth.
“These are the same GTX transceivers used on the FTX FPGAs,” product planner Jean-Louis Brelet told EW.
Dubbed VC5VTX240T, will be applied to high-bandwidth bridging and is the first FPGA to be able to handle a whole 100-Gigabit Ethernet (100GigE) stream, claimed Brelet. Previously two FPGAs have been required.
The family has two chips, the 240T with 240,000 logic cells and 11Mbit of block RAN, and the VC5VTX150T with 148,000 cells, 8Mbit and 40 transceivers.
The firm is touting case studies it said can be handled within a single TXT - a 100GigE MAC to Interlaken bridge in the 240T; and for the 150T: a 40G quad XAUI to Interlaken bridge, a 40G OC-768 to OTU-3 bridge, an SFI5 to 4x SFI4.2 switch and a 32port digital video switch.
In view of intended applications, the chip is down on DSP capability compared with LXT, SXT and FXT family Virtex-5 ICs. “A little bit of DSP is there for telecom applications; error correction benefits from hard-coded multipliers and adders,” said Brelet.
Last week Californian start-up Achronix revealed it is in production of an FPGA with on-chip 10Gbit/s serdes (serialiser/deserialiser) blocks.
Brelet would not be drawn on Xilinx’ future plans for high-speed I/O, but did say: “There is need for 8Gbit/s around PCI-X Gen3 and for 10Gibt/s plus for telecoms applications.”
Based on existing Virtex-5 intellectual property, the head of the family incorporates 48 6.5Gbit/s transceivers giving it 600Gbit/s bandwidth.
“These are the same GTX transceivers used on the FTX FPGAs,” product planner Jean-Louis Brelet told EW.
Dubbed VC5VTX240T, will be applied to high-bandwidth bridging and is the first FPGA to be able to handle a whole 100-Gigabit Ethernet (100GigE) stream, claimed Brelet. Previously two FPGAs have been required.
The family has two chips, the 240T with 240,000 logic cells and 11Mbit of block RAN, and the VC5VTX150T with 148,000 cells, 8Mbit and 40 transceivers.
The firm is touting case studies it said can be handled within a single TXT - a 100GigE MAC to Interlaken bridge in the 240T; and for the 150T: a 40G quad XAUI to Interlaken bridge, a 40G OC-768 to OTU-3 bridge, an SFI5 to 4x SFI4.2 switch and a 32port digital video switch.
In view of intended applications, the chip is down on DSP capability compared with LXT, SXT and FXT family Virtex-5 ICs. “A little bit of DSP is there for telecom applications; error correction benefits from hard-coded multipliers and adders,” said Brelet.
Last week Californian start-up Achronix revealed it is in production of an FPGA with on-chip 10Gbit/s serdes (serialiser/deserialiser) blocks.
Brelet would not be drawn on Xilinx’ future plans for high-speed I/O, but did say: “There is need for 8Gbit/s around PCI-X Gen3 and for 10Gibt/s plus for telecoms applications.”
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