By using a new architecture on first-generation 65nm process products, Tokyo-based DRAM giant Elpida Memory said yesterday that it has developed a shrunken version of its 1-gigabit DDR2 SDRAM that is meant to deliver 20% more chips from a single 300mm wafer, which translates to a 60% increase in chips compared with wafers for a 70nm process, with volume production to begin before the end of this year.

Production will be shared between its Hiroshima Plant, its Taiwan-based Rexchip joint venture and its manufacturing partner PSC, Elpida said.

Elpida also explained that the chip size shrink was made by leveraging a new architecture on first-generation 65nm process products, and estimates that costs for the shrunken version of 65nm products will be approximately 20% less compared to first-generation products.

Further, the Japanese DRAM giant said that as the migration to 50nm process technology leads to higher wafer processing costs due to the need for capital expenditures, the company believes its new 65nm process-based chip will be cost competitive with 50nm products by DRAM competitors.

Also, Elpida said it has reached the final stage of developing a 50nm process and plans to complete work next month, with volume production expected as early as late December, ahead of its earlier January-March 2009 timetable.

The migration to 50nm products with a chip size of smaller than 40 square millimetres should further increase performance and lower costs by making it possible to improve productivity roughly 50% compared with the 65nm shrunken version, Elpida said.

Finally, Elpida believes the chip shrink gives it flexibility to make capital spending decisions and choose manufacturing process composition in response to either prolonged sluggishness in the DRAM market or a relatively early recovery.

By Ann Steffora Mutschler, Senior Editor - Electronic News

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