Cadence Design Systems and Tessera Technologies yesterday announced their collaboration on a new computational-lithography approach aimed at the problems of the 22nm node.

Like an earlier announcement from IBM and Mentor Graphics, the Cadence-Tessera approach abandons hope for extreme UV lithography at this node and instead substitutes more comprehensive OPC and PPC (optical and process proximity correction) and optimisation of the illumination pattern in the stepper.

But where the IBM-Mentor approach appears to put the emphasis on pattern optimisation and only touches on use of a configurable illumination array, the Cadence-Tessera approach emphasizes the use of diffraction masks in the stepper's light source to create custom illumination patterns.

The underlying problem needs little explanation at this point. Lithography engineers and scientists are tying to print features with 22nm critical dimensions using 193nm light. "A lot of the effects that were second- or third-order problems at 65 or 45nm are now major issues at 32 and 22," observed Roy Prasad, vice president of R&D for advanced patterning solutions at Cadence.

"To get adequate pattern fidelity across the entire litho window of dose and plane-of-focus variations, we are building an additional capability on top of our process- and proximity-correction flow: source-mask optimisation."

Prasad explained that in this process - based on computational lithography work originated at the company Digital Optics, which Tessera acquired about two years ago - an optimisation tool examines the pattern data for a critical mask layer; combines it with information about edge tolerances for various structures and with dose and depth-of-focus variation data from the process; and selects an optimal illumination pattern for the stepper.

This pattern may be constrained to be one of the standard patterns supported by the stepper manufacturer, or it may be a custom diffraction mask computed from the printer mask data.

Like other model-based computational lithography tools, source-mask optimisation is an iterative approach, examining a pattern set, proposing an illumination scheme, comparing the estimated results against design requirements, and if necessary selecting a more complex pattern.

But by generating custom patterns computationally instead of just selecting from the stepper manufacturer's list of standard patterns, the approach offers a substantial improvement in process window and, potentially, relaxed rules for chip designers.

Creating a custom illumination mask is no small undertaking, Prasad said. The mask can cost hundreds of thousands of dollars, and unless the fab has a very intimate relationship with the stepper vendor, the mask data require approval from the stepper manufacturer in order to ensure that they do not violate thermal or other constraints for the illumination source. But it is not a novel idea.

"Lithographers have used diffractive elements in the optical path for years," explained James Carriere, senior optical engineer at Tessera. "We are just exploiting the full potential of a technology that is already familiar."

The results, compared with using even the standard off-axis illumination patterns, can be a substantial opening of the process window - especially for layers that have a mix of pitches, widths, and orientations.

Cadence showed data in which a custom illumination mask opened the depth-of-focus window by an additional 50nm above and below nominal - an increase Prasad said could have huge implications for production yield. So on designs that anticipate large production runs - and that means virtually anything that can afford the design cost at 22nm - the cost and time for creating a custom illumination mask will be quickly repaid.

The source-mask optimisation process also has significant implications for chip physical designers. The custom illumination mask makes it possible to achieve greater image fidelity on complex combinations of patterns.

"For the first time, we are able to optimise not just for critical dimensions, but for fidelity of two-dimensional shapes on critical layers," said Tamer Coskun, architect in the Cadence advanced patterning solutions group.

That could mean that, for example, physical designers could considerably relax the design rules on contact layer, allowing for more variation in density and pitch of contact placement. This in turn could make SOC (system on chip) layouts, which typically include a mixture of blocks with different contact patterns, such as large RAMs, CPUs, random cell-based logic, and analogue blocks, far easier to achieve.

The program is currently at an early stage, working with test patterns and feasibility studies. The team hopes to apply the tool to a real full mask layer sometime in the near future, Prasad said. Once the concept and the algorithms have achieved validatation for full layers, Cadence intends to integrate source-mask optimisation into its PPC flow.

In addition, the company plans to include the optimisation tool in the Virtuoso platform, so cell designers can participate in developing an optimal illumination pattern and validate their cell designs using the intended pattern.

This will avoid the risk that portions of a cell library developed by different teams might assume different illumination patterns.

The team expects that the computational load will remain within the range that OPC users expect - perhaps around six hours for a full mask layer. "Design teams expect 24-hour turnaround on mask optimisation, and we believe we will preserve that," Prasad said.

As the various approaches to computational lithography at 22nm begin to emerge, the common thread seems to be the very great difficulty that the industry is taking on in extending 193nm lithography one more time.

The challenge has already triggered major changes in mask optimisation, and it has produced almost a certainty of more restrictive physical design rules. Now we are seeing this need for process awareness bubble up to cell designers as well. The trend may not stop before layout and floorplanning have also been dragged into the battle.

By Ron Wilson, Executive Editor - EDN

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