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Friday 21 November 2008
Components
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|NewsletterMicroprocessors and DSPs
Renesas cuts cost of high efficiency motor design
Tuesday 14 October 2008
Renesas Technology is hoping to change the economics of motor control design by extending the use of fast interrupt microcontrollers to general purpose motor control and inverter design.
Typically, designers are looking for microcontrollers with fast response to interrupts so they can improve the efficiency of the motor control algorithms they use.
Normally, 200MHz performance and a six cycle interrupt response time are only available in a high-end processor, such as the SuperH SH-2A core from Renesas.
The cost of this level of interrupt performance is likely to fall with the company’s decision to use the SH-2A core in a lower cost general purpose flash motor controller, the SH7243.
The fast interrupt response times come from the arrangement of the core’s CPU registers in “banks”, with the 19 registers being mirrored 15 times.
“Using this technique, an interrupt subroutine can use a second set of registers, leaving the current ones ready for use upon return from the interrupt. This means that the registers do not need to be popped onto and back from the stack,” said the supplier.
The SH-2A core, which is a version of the SH-2 core with a superscalar architecture, has two execution units in the pipeline, allowing two instructions to be processed concurrently, and code can be executed up to twice as fast as the CPU clock.
Its Harvard-based architecture ensures that no bus conflicts occur between instruction fetch and data access.
Along with the MTU2 timer unit, with six channels of 16-bit timers and a three-phase PWM capability for electrical motors, an MTU2S peripheral, which is simply a subset of the MTU2, means that the chip can drive two vector controlled industrial inverters simultaneously.
Typically, designers are looking for microcontrollers with fast response to interrupts so they can improve the efficiency of the motor control algorithms they use.
Normally, 200MHz performance and a six cycle interrupt response time are only available in a high-end processor, such as the SuperH SH-2A core from Renesas.
The cost of this level of interrupt performance is likely to fall with the company’s decision to use the SH-2A core in a lower cost general purpose flash motor controller, the SH7243.
The fast interrupt response times come from the arrangement of the core’s CPU registers in “banks”, with the 19 registers being mirrored 15 times.
“Using this technique, an interrupt subroutine can use a second set of registers, leaving the current ones ready for use upon return from the interrupt. This means that the registers do not need to be popped onto and back from the stack,” said the supplier.
The SH-2A core, which is a version of the SH-2 core with a superscalar architecture, has two execution units in the pipeline, allowing two instructions to be processed concurrently, and code can be executed up to twice as fast as the CPU clock.
Its Harvard-based architecture ensures that no bus conflicts occur between instruction fetch and data access.
Along with the MTU2 timer unit, with six channels of 16-bit timers and a three-phase PWM capability for electrical motors, an MTU2S peripheral, which is simply a subset of the MTU2, means that the chip can drive two vector controlled industrial inverters simultaneously.
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