Instead of narrowing the market applicability of its products by
focusing on specific customer needs, the programmable logic
industry would do better to address its fundamental problems: FPGAs
use too much power and are too expensive.
The beauty of the FPGA is that it plays to the economic strength of
the semiconductor manufacturing process, ie, you can turn out a
standard part in high volume and therefore at low cost.
But now, companies like
Xilinx
and
Altera
are asking customers what they want, then pre-programming chips
with those functions. That is a system-on-chip (SoC) company
function. It limits the market applicability of FPGAs.
A better way to go than eroding the fundamental premise of the
programmable logic industry – that it produces the economic Holy
Grail of the standard programmable part – might be to re-engineer
the FPGA to minimise its drawbacks.
A product based on a six-transistor SRAM cell which, additionally,
requires a lot of on-board transistors for programming, is
intrinsically expensive and power-hungry.
The SRAM-based technology, invented by Ross Freeman when working
for Zilog was established as the basic FPGA technology back in 1984
when Freeman and Bernie Vonderschmitt founded Xilinx.
Surely, nearly a quarter of a century later, there must be a better
way to do it?
New memory technologies have emerged since then. Things like MRAM,
RRAM, trapped charge, phase change, even flash. After all, Actel
has built a $60m-a year business out of flash-based FPGA
technology.
Asked if a more energy efficient base technology for FPGA could be
found than SRAM-based cells, Altera CEO John Daane says, “The
reason SRAM dominates the industry, accounting for 99% of the
revenues, is that it is the lowest cost. Basic SRAM cells are the
most efficient and the lowest cost.”
The programmable logic companies may agree that there is not a
better way to do it, and they may agree that a better way to do it
would be a good thing but, when challenged, they say they are not
the people to develop a new technology.
The established FPGA companies say that developing a fundamentally
new technology for programmable logic is the province of the
venture capital-backed start-up company rather than existing
companies.
Venture capital-backed programmable logic start-up companies have
not, however, had a great deal of success, and venture capitalists
are not backing much at the moment.
So, in the absence of a route to substantially improving their
product by other means than conventional shrinks, the companies
have gone down the route of putting more and more custom features
on a chip.
It would be a pity if this were to continue to be the case. With
the programmable logic companies pushing their product further and
further into the realms of the Asic and the SoC, and further and
further away from its genesis as a generic standard programmable
product, FPGA growth is bound to slow, and its margins are bound to
erode.
Could the sea-of-processors approach be a better way to address the
programmable logic market – something on the lines of the XMOS
approach, using multiple DSPs on a chip? Naturally, Daane, does not
think it can.
“The challenge is how to programme it,” he says. “It is the same
challenge as Intel has in programming multicore. The world does not
know how to do it. There is no software that can divide tasks
between cores. The multi-processor approach is limited by the
software programmers who cannot take advantage of more than one
processor core.”
XMOS disagrees. It can program its multicore chips, using C,
extremely efficiently, says company co-founder Professor David May,
co-architect of the Inmos Transputer.
Daane sees the efforts of start-ups to get into the programmable
logic industry as flattering but doomed.
See
Multicore programming explained, by Professor David
May.
“It is flattering that companies want to get into our space,” he
says. “It is a high-growth, profitable market and there are not
many of them in existence. But new companies do not just need an
architecture, they need EDA tools and IP cores.
“There has been $1bn of VC money invested in FPGA in the past 15
years, and $750m of that has already gone out of business.”
Also, Daane points out, a difficulty for new companies trying to
get into the area is that systems companies are cutting down on
their vendor supply lists to provide more efficient, less costly,
procurement procedures.
“At 90nm the cost of Asic development is $30m,” says Daane.
“Assuming R&D cost at 20% of the revenues generated, and
assuming you gain a 10% market share, that means you have to be
addressing a market of $1.5bn. Therefore the justification for Asic
development requires a $1bn-plus opportunity.”
There are not, of course, a lot of $1bn-plus market opportunities,
and the cost of chip development rises with each generation: $55m
at 65nm, $60m at 45nm, $80m at 32nm and $110m at 22nm, so companies
have to find ways out of this financial dilemma.
One way is to increase your market share and knock others out of
the business; another is to add programmability which allows you to
address a larger customer base; another is to use older technology;
another is to use lower-cost designers in China.
“But you don’t get production cost decreases or yield improvements
on mature processes, and you get double-digit salary increases in
Asia but only single-digit salary increases in the West while Asian
currencies are expected to harden – the value of the RMB [China’s
yuan basic unit of currency] is expected to double over the next 10
years,” says Daane.
The result is that fewer Asics are being developed for low to
medium volume infrastructure markets, and fewer start-ups are
getting funded. This, according to Daane, will ensure the growth of
the programmable companies.