Toshiba claims to have made a breakthrough in semiconductor
process technology which could have significance for the future
development of chips at 16nm geometries.
Leading edge semiconductor process technology in commercial
production is
30nm for memory devices and
40nm for logic chips.
The work involved the development of a gate stack and interlayer
with high carrier mobility that can be applied to
metal-insulator-semiconductor field-effect transistors
(MISFETs).
The equivalent oxide thickness (EOT)-scalable high-k/Ge gate stack
with strontium germanide (SrGex) interlayer with high carrier
mobility is a basic technology for MISFETs at the 16nm node and
beyond.
Current MISFETs use silicon for the channel, but physical
limitations of silicon will make it difficult to obtain sufficient
drive current in future scaled down MISFETs.
Germanium can offer higher carrier mobility characteristics, but
has implementation problems.
Development of gate stack structures for Ge-MISFETs is one of the
challenges. There are reports of achieving high hole mobility by
adopting germanium dioxide (GeO2) in the gate stack insulating
layer, but due to its low dielectric constant, there still remains
the challenge of reducing the EOT to 0.5nm, which is required for
the 16nm node and after.
Toshiba
said it has overcome the challenge of fabricating a thin gate stack
while maintaining high hole mobility, by inserting SrGex, a
compound of strontium (Sr) and germanium, as an interlayer between
the high-k insulating layer and the germanium channel.
The technology realises peak hole mobility of 481cm
sq./Volt-second.
Toshiba will continue to develop the technology as an option toward
implementation of Ge-MISFET to 16nm chips and beyond.
The technology will be presented at the 2009 VLSI Symposia in
Kyoto, Japan this week.