Hardware emulators are widely used to debug SoCs that include one or more processors. Although hardware designers are the traditional target market for emulators, software developers often use them for early firmware, kernel and driver development.
The typical connection of a software debugger to an emulator is done with a debug probe connected to the JTAG port of the design, but this solution is very slow because of the serial nature of the JTAG protocol.
This article explores the use of co-emulation transactors to accelerate the connection from the debugger to the target.
Efficiency in SoC design
Many new devices include one or more embedded processors, memory controllers and an array of complex peripherals.
The SoC design flow has adapted to this challenge by parallelising hardware and software design activities so that boot code, operating system support packages and applications are available by the time the device tapes out.
In many designs, functional validation and software availability are on the critical path to release the SoC and there is a need to start software development as early as possible and on increasingly fast platforms.
Hardware emulators can greatly accelerate system integration and hardware validation activities by running test vectors several orders of magnitude faster than RTL simulators. Emulators have therefore become widely used by hardware development and validation teams.
Emulators are often the first platforms to implement a functionally accurate representation of a SoC running at reasonable speed. Therefore, software development teams have become interested in them to run their SoC bring-up firmware, operating system boot code, kernel and drivers.
Not only do emulators enable them to perform this critical activity earlier in the design cycle, they also provide the SoC visibility to resolve software/hardware integration issues.
Development on emulators
Since emulators are scarce resources (and a significant capital asset), they need to be used efficiently. Efficiency may be achieved, for instance, with processes and tools that reduce the “emulator time” required to solve particular problems.
When using emulators, software developers should use tools that provide full processor control: set breakpoints, single step through the code, view and change the contents of memory and memory-mapped peripherals, etc. Complex processor features, such as virtual to memory address mapping and hardware cross-triggering, must be handled by the tools automatically to save development time.
Most embedded processors include interfaces to allow the connection from a software debugger. These interfaces are accessible on the JTAG or serial debug port of the SoC.
The connection between the software debugger and the SoC is done with a debug probe.
The same debug probe used to connect to a SoC can also connect to a processor synthesised on a hardware emulator via the emulator’s in-circuit emulation (ICE) interface.
Unfortunately, this JTAG debug interface is slow and debug operations such as memory download and single stepping take an unacceptably long time. This limitation is currently hindering the usability of emulators as software development platforms.
Accelerating development
Depending on the processor synthesised on the emulator, different debug speeds can be achieved.
For example, the debugger connection to ARM9 and ARM11 family processors is comparatively slow. These processors have native JTAG debug interfaces that can be daisy-chained.
Because of the nature of the JTAG protocol, the JTAG clock (TCK) is driven by the debug probe. In order to synchronise TCK with the processor clock TCK needs to be sampled with a chain of flip-flops, which effectively limits its speed to about 100KHz on emulators.
The debugger connection to Cortex processors on emulators is faster, as they have a parallel debug interface.
The SoC normally includes a debug access port (DAP) which provides an interface between JTAG and the internal debug bus.
In the DAP, the synchronisation between TCK and the system clock is only required when a 32-bit access goes to the debug bus. In practice this means that on emulators the JTAG interface can run at up to 500kHz, a five-fold increase compared to ARM9 and ARM11 processor family-based systems.
However, this debug connection is still very slow compared to the 10-50MHz JTAG supported by Asics.
Because of the speed limitation of emulators the TCK frequency cannot be increased further. However, a faster debug connection may be achieved by bypassing the JTAG interface and implementing a direct connection to the debug bus.
A direct connection can theoretically provide a 50-fold debug speed increase, as each 32-bit access on the debug bus is done in a single bus clock cycle instead of 50 JTAG clock cycles. The debug connection speed therefore becomes equivalent to 25MHz JTAG. The speed of the processor, memories and peripherals running on the emulator remains the same.
Javier Orensanz is product manager at ARM and Richard Pugh is product marketing manager at Mentor Graphics.