More than one in three design organisations expect to begin using C
synthesis to generate RTL code by the end of 2009.
This measurement is based on responses from 800 chip design
professionals who completed an anonymous, independent survey
sponsored by Mentor Graphics.
It represents a major jump from the one in seven who said they were
using C synthesis for RTL design implementation in 2008.
This statistic is a compelling indicator that C synthesis, also
known as high-level synthesis, is finally gaining worldwide
momentum. The survey respondents included hardware, software and
firmware designers targeting Asics and FPGAs across the globe,
working on applications such as wireless, image and video
processing, networking, and data communications.
The top three reasons driving these design teams’ use of C
synthesis were: reduced verification, faster time to RTL, and fewer
engineering resources. Faster time to RTL was cited by 64% of
users.
This is perhaps the most widely appreciated purpose because the
promise of C synthesis moving design automation up another level of
abstraction from RTL synthesis has been touted for years.
However, reducing verification effort came slightly ahead of
time-to-RTL, with 68% of the survey respondents citing faster
verification or fewer bug fixes as their primary reason to adopt C
synthesis.
This makes perfect sense. Verification is the major design
bottleneck today. By modelling at the C level, engineers can verify
design functionality far more rapidly and exhaustively than they
can with RTL code.
Design teams can further magnify the verification benefits by
selecting a flexible, compact C source such as ANSI C++, and
ensuring that the C synthesis tool maintains the deterministic
behaviour of their C source. Combining these benefits with the fact
that C synthesis eliminates the bugs in RTL that are typically
introduced during manual RTL creation offers substantial gain – we
have seen up to a 70% overall reduction in verification
effort.
Fewer engineering resources was the third major justification for
adopting high-level synthesis, cited by 31% of respondents. The
economic climate over the past year has forced organisations to
consider every measure to do more with limited resources.
In this economic climate engineering groups are keenly motivated to
determine which C synthesis tool will allow them to deliver more
gates per engineer in less time. I encourage organisations to
include in their C synthesis tool evaluations the features that
will ease deployment and help achieve immediate time savings.
These include whether there are intuitive, interactive user
interfaces allowing designers to retain control over the synthesis
process; an easier learning curve; and how rigorously the EDA
vendor supports a flexible, compact design input language such as
C++ that conforms to industry standards.
Commercial behavioural synthesis tools have progressed in the two
decades since their initial promise of providing higher abstraction
chip design. Companies are slashing their project completion times
by transitioning from manual RTL design to automated C synthesis.
As C synthesis deployment accelerates in the coming year a
considerable part of the gains will come through incorporating a
verification strategy. This will help designers reap the full and
long awaited rewards of C synthesis.
Shawn McCloud is product line director at
Mentor Graphics