NXP could be planning to combine the ARM Cortex-M0 and M3
processors cores in a new multicore device.
NXP is already working on new versions of its Cortex-M0 based
microcontroller, the LPC1100.
It is looking at adding on-chip analogue circuits aimed at a very
low cost device for smart metering applications.
Another direction the company is exploring is the development of a
multicore version.
“Adding a full function analogue front-end to M0 would be
inherently low cost for industrial applications like smart meters,”
said Geoff Lees, v-p and general manager of NXP’s microcontroller
business.
It is not just very low power MCUs which Lees has in mind, he
sees the Cortex-M0 core forming the basis of a family of MCUs
ranging in performance which could also include multicore
versions.
One option being investigated is adding the M0 to another high
performance core such as the Cortex-M3.
“Multiple cores could be used for power management and
house-keeping functions in smart meters for example, “said
Lees.
NXP announced the first Cortex-M0 based MCU earlier this year
and Lees says that the part will be available in volume
“imminently”. This is likely to be next month.
See:
ARM's Cortex-M0 processor - how it works
Lees also confirmed that there would be open-source design
support for M0 through an Eclipse tool, probably the Texas
Instruments tool.
This will be in addition to the existing ARM development support
from Keil and IAR.
This will be offered via the online development environment NXP
has been working on with ARM.
Called "mbed" the website will launch with hardware and software
support for the NXP LPC1768 ARM Cortex-M3 processor-based MCU.
But support for
LPC1100 will be added in the near
future.
Lees sees that offering an open platform is important for
microcontrollers such as M0.
“We want it to be open to all vendors, designs could even be
made public,” said Lees.
The big selling point of the Coretx-M0 based devices is low power
operation.
This is inherent in the design. Power consumption can be
optimised in the M0 with the use of its 11 differ power domains.
The ARM8 core had just three.
An important power saving feature of the M0 is the use of the
Thumb instruction set. M0 is a von Neumann design executing a
modified form of the Thumb instruction set.
“It is not intuitive to see 32-bit code as smaller that 16-bit,
but Thumb is compressed code,” said Lees.
The same instruction set has been used in the ARM7 and ARM 9
cores, but an important feature of the Cortex-M0 is that the
decoding of 16-bit instructions into 32-bit is hardwired into the
core.
“The result is the M0 is a quarter the power of the M3. It is a
key power saving feature,” said Lees. “
The result is an MCU with a power/performance of under
150µA/MHz.
In comparison the Cortex-M3 based LPC1300 consumes approximately
200µA per MHz.
“We are working on getting M0 under 150µA/MHz, the target in the
short term is 100µA/MHz and I believe 50µA/MHz is achievable in the
longer term,” said Lees.