MIPS Technologies has introduced two
cores and a 16bit instruction set.
The M14K and M14Kc have the same 1.5DMips/MHz performance as the
firm's existing 4K series, with which they share a five-stage
pipeline, but with code density improved by 35% compared with the
4K.
"We have gone to the MicroMIPS instruction set which is a
re-encoding of MIPS32 and MIPS64 instructions," MIPS director of
product marketing Mark Throndson told Electronics
Weekly.
He estimates that Linux code running on a 14Kc will be over 30%
smaller than Linux prepared for a 4K.
The 14K is aimed at automation and control in offices, cars and
industry, whereas the Linux-capable Kc is destined to run more
complex operating systems in home entertainment boxes, consumer
networking modems and routers, and portable entertainment
devices.
MicroMIPS is not purely 16bit and includes 15 new 32bit
instructions alongside 39 new 16bit instructions. There are also 64
bit instructions, which are not implemented in the M14 cores.
Both the M14K and M14Kc have dual instruction decoders so that
they can run both MicroMIPS code and legacy MIPS32 code.
There are several significant changes compared with 4K
cores.
For example: interrupts are now hardware based and twice as
fast, taking 21 cycles, and interrupt chaining is executed by a new
IRET instruction.
Debug and trace features have been added.
"We looked at the most useful features in the 24K [high-end]
cores," said Throndson, "and added two performance counters to the
M14K, and support for programme counter and data address
sampling."
There is also a trace for function calls with an exceptions
option and delta cycle tracing.
The debug channel is bi-directional JTAG, is interrupt driven,
and includes FIFOs.
Another change is the addition of an instruction pre-fetch
buffer has accelerated execution out of flash by up to four times
(4x with a 100% hit rate at 100MHz).
The Linux-enhanced M14Kc is superset of the earlier MIPS32 4KEc
core.
As well as the M14K features, it also has a cache controller,
translation look-aside buffer (TLB), and AHB Lite bus interface -
although this last feature can also be included in a M14K
implementation.
Like other MIPS cores, licensees can add their own
instructions.
On TSMC's 90G Svt process, a speed-optimised M14K is projected
to run at 295MHz (442Dmips), occupy 0.51mm2 and
dissipate 120µW/MHz.
The same core area optimised will, said MIPS, achieve 193MHz
(290DMips), 0.21mm2 and 60µW/MHz.
On TSMC's 90 SVt process, the speed optimised M14Kc figures are:
322MHz (483DMips), 0.82mm2 and 150µW/MHz, or 194MHz
(291DMips), 0.37mm2 and 80µW/MHz when area
optimised.
For SoC development, an FPGA-based board called SEAD-3 is
available which has multiple FPGA sockets to support the MIPS core
separately from customer intellectual property.
Two simulators exist: cycle accurate CASim and instruction
accurate IASim.
The M14K
The M14Kc