FPGAs have been used in satellite design and other space
payloads for more than a decade.
The need for higher levels of processing power is a size and power
optimised circuit has prompted Actel to add hard-wired DSP clocks
to its existing hi-rel FPGA fabric.
When adding MAC blocks to the FPGAs for use in a high reliability
application such as space systems, Actel implemented a complete
redesign of the DSP blocks to incorporate the necessary level of
circuit protection.
The first technique is the use of triple module redundant
flip-flops “These are configured with majority voting,” says Ken
O’Neill, director, high-reliability product marketing at
Actel.
“So correct operation takes place even when only one of the three
flip-flops erroneously changes,” says O’Neill.
The other issue is providing protection against single event ion
upsets. This becomes a serious issue as clock rate increases.
Actel’s architecture addresses this with parallel paths within the
mathblocks which are running at the highest speeds.
Each mathblock is capable of operating at 125MHz across the full
military temperature range.
There is a fixed delay between the paths and the data on each is
compared to distinguish between true transitions and glitches. The
glitches will only appear on one path.
These techniques have been used in maths block of Actel’s recently
introduced RTAX-DSP range of space devices.
RTAX-DSP FPGAs feature up to 120 multiply-accumulate DSP math
blocks, protected against radiation-induced single event upsets
(SEU) and single event transients (SET).
The RTAX-DSP FPGAs use the same 0.15µm UMC wafer fabrication
process and the same antifuse programmable interconnect technology
that are used in the industry-standard RTAX-S FPGA family, which is
now accumulating space-flight heritage on as many as nine space
programs.
But why is it necessary to send DSP blocks into space in the first
place? After all Actel has been shipping space-hardened FPGAs since
1992.
“The significance here is that adding the DSP, the hardwired MAC
blocks, to the FPGA makes more efficient use of the silicon for the
data processing functions,” says O’Neill.
The trigger is the need for higher signalling and data transmission
bandwidths.
A typical narrowband comms circuit will have as many as three FPGAs
for filtering and extraction. The move to higher bandwidths
increases that number to impractical levels.
The new devices will offer densities of up to four million
equivalent system gates and 840 user I/Os for space-based
applications.
Embedded DSP mathblocks feature 18 bit x 18 bit multiply-accumulate
blocks enabling efficient implementation of DSP building blocks,
such as finite impulse response (FIR) filters, infinite impulse
response (IIR) filters, and fast Fourier transforms (FFT).
So the dedicated processing performance of DSP makes more efficient
use of the silicon, which a key factor when designing a satellite
payload.
Optimising power consumption is the other factor as satellite
systems are traditionally battery and solar-powered.
Actel is working specific IP blocks these include a finite impulse
response filter. A fast Fourier transform filter is planned.
According to O’Neill, the first fully qualified flight units will
be available in the second half of next year, and there are
prototype devices for demonstrating and validating designs.
The RTAX-DSP prototype devices have the same pin assignment,
mechanical footprint and identical timing properties across the
full military temperature range (-55°C to 125°C) as their
space-qualified counterparts.
“The availability of RTAX-DSP prototype FPGAs enable designers to
demonstrate their RTAX-DSP designs in hardware across the full
operational temperature range,” says O'Neill.