Lattice Semiconductor has announced version 8.0 of its ispLEVER
FPGA design tool suite, which is used for the design of high speed
double data rate (DDR) interfaces for the LatticeECP3 FPGA
family.
Lattice Semiconductor has
also said that it will collaborate with Slovenia-based Beyond
Semiconductor in the development of compiler tools for its soft
processors, the LatticeMico8 and LatticeMico32 embedded
microprocessors.
The IPexpress tool can be used to generate the HDL for the most
appropriate generic DDR interface based on user requirements such
as direction, speed and bus width.
This HDL has been specifically designed and validated for high
performance, robust operation.
There is now automatic interface code generation to increase design
productivity and reduce coding errors, as well as enhanced timing
analysis that provides more transparency to circuit timing
details.
To support analysis of the interface between the IO and fabric
clock domains, the trace static timing analysis report has been
enhanced to include a “Timing Rule Check” section that specifically
analyzes these clock domain transfers. This is done automatically
and does not require users to define additional timing
constraints.
The IPexpress tool can now also optionally generate the complete
I/O-specific circuitry for proprietary DDR memory interfaces,
allowing designers to focus solely on the controller logic of their
DDR1 and DDR2 DRAM interfaces.
See:
Top 10 embedded reference designs