Lattice Semiconductor has announced a Serial RapidIO 2.1 soft core for its ECP3 FPGA family.
Supplied by Praesum Communications, the core supports 1x, 2x and 4x lane configurations at up to 3.125Gbit/s 
lane speeds.
Lattice has also licensed the core from Praesum, and has full rights to use and sub-license it.
"RapidIO has won broad acceptance in wireless infrastructure applications, where it is used as a primary interconnect for DSP clusters in baseband processing," said Lattice. "The combination of core and FPGA will allow customers to develop infrastructure solutions for 3G, LTE and WiMAX.
The core implements physical layer, 
transport layer, maintenance transaction handling and error management extensions, as well as providing infrastructure support for external logical layer functions.
It supports software implementations of control plane oriented functions such as doorbells and messages, and is backward compatible with the v1.3 specification.
The ECP3 FPGA family has five devices with multi-protocol 3.2G SERDES, DDR1/2/3 memory interfaces, and cascadable DSP slices.
Up to 6.8Mbit of embedded memory is included, up to 586 user I/Os, and logic density varies from 17,000 to 149,000 look-up tables.