Belgian lab IMEC is to use Synopsys' finite-element method tools for characterising through-silicon vias in 3D stacked IC technologies.
Die to die stacking is seen as one way to reduce device size and, by cutting interconnect capacitance, reduce power consumption while increasing chip-to-chip communication bandwidth.
It also allows devices to contain silicon optimised for different circuit types: DRAM and logic, for example.
The research will be a team effort based at IMEC where silicon wafers with test structures will be manufactured and tested.
"This collaboration affords us the opportunity to validate the simulation tools for addressing the emerging 3D stacked IC technology," said Howard Ko, general manager of Synopsys' silicon engineering group.
"It will speed up the development of through-silicon via technologies and will in turn facilitate the adoption of 3D stacked ICs in the semiconductor industry," said IMEC CEO Luc Van den Hove.