Xilinx is attempting to break the mould with its latest generation Virtex-7 FPGAs.
The underlying aim seems to be to put lower power FPGAs into mobile devices.
There are interesting changes from the supplier’s previous Virtex 6 and Spartan 6 families.
There are new product family names, a single architecture, common intellectual property (IP) across all families and the devices are fabbed on the TSMC 28nm HPL process.
But behind it all is the supplier’s, perhaps any FPGA supplier’s, biggest attempt yet to move FPGAs away from their traditional role as an Asic replacement.
FPGAs are a higher cost and more power thirsty programmable alternatives to glue logic and Asics in data processing, networking and video systems.
Big reductions in power, both standby and dynamic power, along with more cost effective use of IP are hoped to move Virtex-7 and its associated families into battery-powered devices and lower cost consumer products.
The new Artix-7 family of low-end FPGAs will be the company’s first sub-1W device. “The hope is it will get us into handheld applications,” said Vin Ratford, senior v-p worldwide marketing fro Xilinx.
“It will open up markets in consumer, automotive and industrial wireless we could not be in before,” said Ratford.
Xilinx also thinks it can change the view of FPGAs in high end networking and data processing systems, already a core market for its products.
“At the high end the Virtex-7 has the performance and power efficiency to compete with network processors in switching routing function and not just as a bridging device,” said Giles Peckham, European marketing director for Xilinx.
Architecturally, Xilinx has moved away from its traditional product range based on two different devices - Virtex and Spartan.
It will now offer a single FPGA architecture based on 28nm process technology which will be sold in three families, the high end Virtex-7, the lower power Spartan replacement called Artix-7 and in between the Kintex-7 which is essentially the replacement for Virtex-6 designs.
Design elements and IP will be common to all families, making it easier to move designs from one device to another.
Xilinx has used a modified, under-clocked, version of TSMC’s 28nm HPL process to improve static power efficiency. It has also modified transistor design, extended clock management and lowered on-chip memory voltages to reduce static power by as much as 65% compared with the previous generation FPGAs for equivalent performance.
As a result the Artix-7 family should have 50% lower power and 35% lower cost compared to the Spartan-6 family, said Peckham.
While the Kintex-7 family aims to match the performance of Virtex-6 devices with 10.3Gbit/s or 6.5Gbit/s serial interfaces, at lower cost and half the power.
“A target application for Kintex-7 is multimode wireless systems so there is CPRI/OBSAI interface support and 491MHz performance,” said Peckham.
Today this is Virtex-6 territory and Peckham claims a 70% price reduction is possible with the new devices. “There is also a 48% reduction in power for the same performance Virtex-6 device,” said Peckham.
The ISE Design Suite software will support these 7-series FPGAs with first silicon due to sample in early 2011.
See: FPGA to outgrow logic sector for 5-10 years, says Gavrielov
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