Most of today’s engineers would include knowledge of some form of programmable logic in their armoury of design techniques. With Asic design starts widely reported to be in decline, it is becoming increasingly necessary to have some methodology in order to evaluate suitable devices for a new design.
Programmable logic has come a long way from the early form of simple programmable array logic (PALs) to the level of integration that is available today. The increased degree of complexity of current product offering from the various vendors of programmable devices makes it difficult for design engineers to differentiate how a particular device would operate in a real time environment.
With application specific devices the performance of the product is usually well documented and the product specification details most of the critical parameters, this is not necessarily true of programmable devices where variations in how a design is instantiated within the device can have repercussions on the overall performance. Routing factors within the device and in the case of high speed signals PCB layout and other variables can play an important part in the final implementation.
Lattice Semiconductor’s MachXO family of non-volatile infinitely reconfigurable programmable logic devices (PLDs) is a good example of such a device, designed for applications traditionally implemented using CPLDs or low-capacity FPGAs. It is intended for a broad range of applications that require general purpose I/O expansion, interface bridging and power-up management functions.
The family of device’s offer the benefits of increased system integration by providing embedded memory, built-in PLLs, high performance LVDS I/O, remote field upgrade (TransFRTM technology) and a low power sleep mode, all in a single-device.
A design engineer and his management will certainly not wish to expend a lot of energy and resources specifying a design which is solely to be used for evaluation purposes, they will wish to have a solution that decreases the time to revenue not a prolonged product selector evaluation procedure with the additional cost. The methods and procedure must be relatively fast, efficient and cost effective.
The question now becomes: how can one evaluate how such a device will perform a given task. One method that can be adopted is to use a manufactures evaluation board to exercise the selected device with a known reference design and measure its performance.
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The major issue with this approach is determining what design and procedure will help in evaluating the suitability of such device for the final task it is intended to perform.
One such solution for the MachXO device is the Mini development board; it comes with the MachXO LCM02280 device already installed on the board. The parametric performance of this device will be typical for the whole device family.
In order to get the engineer stated quickly the device has been factory pre-programmed with a miniature typical system-on-a chip design that integrates multiple “soft” components such as the LatticeMico8 8-bit microcontroller, and peripheral controllers for on board SPI memory controller, SRAM controller, UART and I2C master with a WISHBONE interconnect.
The evolution board also contains banks of LEDs and switches along with SPI Flash memory, SRAM and an I2C Temperature sensor. The board can be controlled with the on board switches and a menu driven interface via a Windows or Linux terminal and be programmed over an RS-232/USB link. The board is powered by the USB interface and therefore does not need an external power supply.
Once the Mini SoC demo is running on the board, one can easily access the reference design source code including the HDL, firmware, and the design tools required to quickly customise the design application.
An on-board I2C bus connects the MachXO to a temperature sensor. The mini SoC demo uses the LM8 microcontroller to sample the temperature sensor over time, log the results on to the on-board SRAM and display the results on the LED array or terminal interface running on a PC via a RS-232/USB link. A SPI bus is also provided on the board that connects the MachXO to a 2Mbit non-volatile SPI Flash memory. The Mini SoC demo uses the LM8 to control transactions between the SRAM and the SPI Flash Memory.
The evaluation board allows the engineer to measure the drive strength, speed and signal switching characteristics of the installed device.
Once the engineer is familiar with the complete reference design he or she can then use the development tools to make changes to the design in order to see what the effect is on the overall performance.
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Lattice’s free ispLEVER development tools offer a comprehensive design environment and includes everything needed for design entry, synthesis, map, place and route, I/O planning, simulation, project management, device programming, and more. Synthesis and simulation tools from Aldec and Synopsys are included with ispLEVER.
The costs associated with current state of the art manufacturing are the driving force for some form post manufacture programming capability. The provisioning of tools for the evaluation and programming of such devices are a key issue to their early adoption.
Doug Hunter is v-p marketing at Lattice Semiconductor