AMD is joining FPGA firm Xilinx and design tool specialist Celoxica to discuss the potential for hardware acceleration of microprocessors using tightly coupled co-processor devices at next month’s Embedded Systems Conference in the San Jose, California.
According to the firms, previous attempts at off-load into parallel and programmable hardware architectures have fallen short of the mark due to technical barriers, price or lack of suitable design tools for development and debug. They are expected to present a “commercially viable solution” based on FPGAs and ESL design.
At the heart of the proposal is AMD’s Opteron processor with its Direct Connect Architecture and native HyperTransport technology used with a Xilinx FPGA, supported by Celoxica’s programming environment, to create a “cost effective” accelerated computing platform.
“AMD64’s Direct Connect Architecture and HyperTransport technology, can provide a tightly coupled co-processor expansion capability and address the communications bottleneck that has negatively impacted compute off-load to co-processors in other solutions,” said Doug O’Flaherty, division manager for Acceleration Strategy at AMD.
According to Xilinx, the computing industry is beginning to use the potential of Virtex-4 FPGAs as a co-processor to microprocessors, such as the AMD Opteron.
“Algorithms embedded in large applications can be greatly accelerated which can in turn improve the overall compute performance for systems in the scientific and medical imaging markets, as an example,” said Krishna Rangasayee, senior director of Vertical Marketing and Partnerships at Xilinx.
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