Akya, the re-configurable logic specialist, has joined Cadence’s System Realisation Alliance aimed at simplifying the flow from high-level design synthesis to chip designs.
“We’re particularly grateful to Cadence for having the far-sightedness to co-ordinate an industry body such as this,” says Akya CEO Colin Dente, “we’ve been saying for a while that one of the main barriers towards innovation is lengthy design and verification times. This is the ideal way to reduce design and verification times, thus bringing more complex and differentiated products to market.”
Akya’s contribution to the aims of the Alliance aim of accelerating and simplifying the process of designing silicon is its ART DRL IP technology.
Akya sets out to simplify the process of moving from high-level chip synthesis in languages such as C to realised designs. As well as the development of new tools, this will hinge on the development of advanced design flows such as TLM-driven design – one of the core drivers for the Cadence System Realization Alliance.
The Alliance aligns members to improve productivity in developing and verifying systems including software and silicon. Members provide tools, design and verification IP, services and training.
Key objectives are:
- Increasing tool usability and interoperability.
- Defining open methodologies built on industry standards.
- Enabling the creation of reusable system-level design and verification IP.
- Proliferating methodology usage through training.
- Simplifying methodology adoption and assisting customer success through services.