The European Commission has established a taskforce to devise new ways of designing future microchip memories that take into account the variability and unreliability of nano-scale transistors.
The 'Tera-scale Reliable Adaptive Memory Systems' (TRAMS) consortium includes: Intel Corporation Iberia, Interuniversitair Micro-Elektronica Centrium vzw, the University of Glasgow, and the Universitat Politecnica de Catalunya, and is financed through the EU's Framework Programme 7 (FP7) science research fund.
Leading the University of Glasgow's involvement is Professor Asen Asenov, of the Department of Electronic and Electrical Engineering, an authority on the variability of Complementary Metal-Oxide Semiconductors (CMOS) transistors and microchips.
"Tera-scale computing will transform the power, performance and functionality of personal computers, phones and other electronic devices as well as large computing facilities such as data centres," said Asenov.
"However, if we are to continue to shrink the size of transistors in order to develop such powerful circuits, we need fundamentally new approaches to circuit and system design that can take account of the variability within transistors.
"We hope this project will result in new chip design paradigms for building reliable memory systems out of unreliable nano-scale components cheaply and effectively, heralding the era of tera-scale computing."
Part of the project is simulation software developed by Prof Asenov through an earlier £5.3m Engineering and Physical Sciences Research Council eScience pilot project called NanoCMOS.
Glasgow is setting up a company called Gold Standard Simulations to exploit this technology which will be important for the work of the TRAMS project, with all device design and simulation work being conducted at Glasgow, states the University.
In investigating design possibilities for future microchips, the team will focus on future generation of CMOS microchip technologies, it says - which comprise transistors less than 16 nanometres in size (by comparison a human hair is around 100,000 nanometres wide). The transistors will apparently be designed and simulated exclusively by Glasgow.
According to the University of Glasgow, the TRAMS consortium will also consider what are known as 'Beyond CMOS' technologies; nanowire transistors, quantum devices, carbon nanotubes and molecular electronics, which are expected to be as small as five nanometres.
The project is expected to last three years.