Samsung Electronics has developed its first all-DRAM stacked memory package using a ‘through silicon via’ (TSV) technology, which it claimed will radically reduce the size and power of memory packages.
The wafer-level-processed stacked package (WSP) consists of four 512Mbit DDR2 DRAM chips which will be used in a 4Gbyte DIMM.
As an alternative to wire bonding, Samsung’s WSP technology forms laser-cut micron-sized holes that penetrate the silicon vertically to connect the memory circuits directly with a copper (Cu) filling, eliminating the need for gaps of extra space and wires protruding beyond the sides of the dies.
Inside the new WSP, the TSV is housed within an aluminum (Al) pad to escape the performance-slow-down effect caused by the redistribution layer. Due to the complexity of DRAM stacking, this represented a much more difficult engineering feat than that accomplished with the first WSP, announced last year involving NAND flash dies.
Samsung said the stacked package design will support next-generation computing systems in 2010 and beyond.