The analogue and RF chip market has gained a set of verification
tools from Berkeley Design Automation, an EDA start-up.
BDA's products are based on research from the University of
California at Berkeley and the University of Illinois. Core to this
is the ability "to characterise the nonlinear, stochastic,
time-varying behaviour of complex analogue and RF circuits", said
the firm.
The first product is called PLL Noise Analyzer. It can analyse
phase noise and jitter in PLLs, identify the top source of noise
and check sensitivity of the circuit. It integrates with existing
analogue design flows.
"Analogue circuits are pervasive today, even in the most
'digital' of designs," said Dr Ravi Subramanian, BDA's president
and CEO. "Our customers have told us that the greatest challenge in
the design process today is to reduce the rate of silicon spins
required to achieve volume production for these analogue-rich
ICs."
The firm said its tools have already been used in 35 designs,
from 0.25µm to below 90nm.
www.berkeley-da.com