Earlier this week, NXP introduced the fastest Cortex-M3-based microcontroller yet, the 150MHz LPC1800.
Electronics Weekly finds out how the firm achieved the speed, more about the processor's novel peripherals, and learns what to expect from NXP's forthcoming Cortex-M4 DSP-microcontroller.
Although LPC1800 is made on a 90nm process, finer than its predecessors, its speed not simply from a shrink of the earlier LPC1700.
"Preliminary CoreMark score is greater than 1.9/MHz, compared with 1.7/MHz for the 1700," Geoff Lees, general manager of NXP's microcontroller division, told Electronics Weekly.
Much of this increase has come from the way the core talks to flash memory - like the 1700, it can run at full speed direct from its 1Mbyte flash - and an expansion of busses that allows all on-die bus masters to have simultaneous access to memory and peripherals.
To allow its flash to keep up with the processor, wide busses are used.
"One of the things that helps the 1800 is the 256bit wide flash. It was 128bit wide in the 1700 which only allows 4x32bit instruction reads in a single cycle," said Lees, adding: "The move to 256 bits on 90nm gives us great overhead for the future to 200MHz operation."
This is not the first time NXP has used a 256bit flash bus.
The earlier ARM7TDMI-based LPC2000 employed architectural belt-and-braces to guarantee it would meet is design targets.
"It had dual 128bit flash," explained Lees. "This was great for performance to 120MHz, but we found we didn't need it so we took it out."
Also compared with the 1700, instruction pre-fetch is more intelligent in the 1800.
A built-in algorithm decides to pre-fetch instructions if the core is running fast, or to wait until the flash current buffer is nearly empty if the core is running slower.
"This saves us a lot of power," said Lees.
In highest performance mode, the algorithm can pre-fetch more than eight words and, if there has been a lot of branch activity, saves branch trails as well.
The LPC2000 could also save branch trails, but only one compared with multiple trails in the 1800.
For high reliability applications, on-chip flash can be operated in a front-back mode where flash is split in two, with all code copied identically onto each half.
This allows the so-called 'golden copy' method of in-field memory update - insisted upon my automotive users - where the controller executes entirely from one half of memory while the other half is re-written.
The penalty is halving the amount of available flash, so the 'golden kernel' technique, where only the kernel is duplicated at the bottom of each page, can also be implemented.
RAM access has also come in for scrutiny.
"The ARM architecture fetches data frequently," said Lees. "If the data is in flash, the LPC1800 has an option to save more than one data buffer - up to 8x32word, where the LPC2000 was 4x32."
In February, ARM announced the Cortex M4, an integer DSP-enabled super-set of the M3. Freescale, NXP and ST have announced M4 products.
According to Lees, LPC1800 marks the first appearance of technology that will appear in NXP's Cortex M4s when they arrive.
"The M4 can run up to 250MHz with same buffer," said Lees. "Above 250MHz, we can go back to LPC2000 architecture and have 2x256 interfaces interleaved for 512bits."
With two flash interfaces, the second flash pre-fetches another eight words in a half cycle, he explained, giving a "small but significant improvement" in throughput.
Where the 1800 M3 and M4 have an advantage over the LPC2000 is that they have a multi-layer AHB bus.
Originally tested out in the ARM968-based LPC2900 series, the multi-layer bus uses a cross-bar switch and allows RAM to be treated as multiple blocks for simultaneous access by the core and any peripherals that can also act as bus masters - eight potential masters in all.
All this connectivity means a lot of metal tracks across the die, which Lees pointed out is made possible by having seven metallisation layers, including two over memory areas.
The ability to treat flash as two halves allows data/instruction partitioning which can help the M3, and will be of even more significance with the M4.
"If all data is kept in one bank and all instructions in the other, there is a 10% performance improvement," said Lees. "This is very important for the Cortex M4 because, with DSP, it is very common to have data from an array of flash - for example: voice clips or waveforms for power generation."
"The LPC1800 is the platform for the M4 memory interface and peripherals," said Lees. "We have increased RAM on M4 devices beyond 200k, and you will see some M4s in a couple of weeks."
Two of these peripherals are significant introductions.
The first is an SPI interface that can handle quad-mode operation for off-chip 8pin flash ICs.
"Quad-mode has emerged over last 18 months," said Lees. "After the initial handshake, the pins of the SPI interface are re-purposed into four data lanes that each support 80Mbit/s which is a total of 40Mbyte/s. So on a cold re-start you can transfer entire SPI flash in 1/3 to 1/100 seconds into on-chip SRAM or exterior RAM."
He claims NXP has tested quad-mode operation with 80 different flash chips from six supplier.
The other significant peripheral is the so called 'state configurable timer sub-system' (see diagram below).
Devised by NXP architecture manager Rob Cosaro, this is essentially a programmable general purpose state-machine combined with a timer.
The state-machine's eight inputs and 16 timer outputs are bough out to external pins allowing it to interact with external hardware.
Once the state-machine has been initialised by the CPU, and providing the required number of states fits into the 16 provided, the state configurable timer becomes autonomous and requires no further CPU intervention.
A partner block decodes up to 16 events - from outputs, inputs and states - to drive the state-machine from state to state.
According to Lees, there are enough resources to build quite sophisticated functions including a brushless DC, stepper or AC induction motor controller; or a serial interface for DALI or LIN.
Fizzim, the finite state-machine tool, can be used to design the machines.
"We intend to build-up library," he added.
The first M3 LPC1800s will be in 100pin BGA with 100kRAM no flash as they are intended to work with external 8pin SPI flash.