Simon Bloch of Mentor looks at how electronic system level design tools can quickly get data intensive designs to market
Recent analyst forecasts indicate that the market for electronic system level (ESL) design tools will triple in the next three years.
The reason is simple - design complexity. Even taking into account the growing reliance on reuse and platform-based design, Gartner Dataquest estimates that 30 per cent of the gates in next-generation designs will still need to be specified and verified. What is more, the convergence of computing and communications is driving growth in algorithm-dominant applications such as video/image processing.
The extreme complexity of these designs has pushed RTL-based flows to their limits. Consequently, designers of Asics and FPGAs are feeling the pressure to move to a higher level of abstraction to cope more efficiently with exploding gate counts and design complexity.
ESL offers a way to move beyond RTL to a higher level of abstraction.
The ultimate vision for ESL is to automate the concurrent creation of both the hardware and software from a single, high-level system specification. Many EDA companies are focusing on the hardware domain first, developing systems for design, synthesis and verification tasks.
Complex electronic systems include blocks created in three different design styles, each with specific demands. Consequently, ESL design is comprised of three different methodologies – algorithmic, processor/memory (bus-centric) and control logic – each of which is evolving independently.
For control logic - probably the least mature ESL methodology - many hardware designers are searching for a more efficient way to implement a finite state machine.
Processor/memory-centric designs encompass hardware, software, busses – an entire system. On-chip communication is crucial in this area and designers need to raise critical design decisions, such as hardware/software partitioning, to a higher level of abstraction before committing to RTL.
In algorithmic-centric designs, engineers need to design and verify an optimal implementation as quickly as possible. With no processor involved, these data path applications are not required to consider bus performance issues that consume other methodologies.
The design team can avoid the process of rewriting and retesting source code when making architectural changes and designers can easily explore alternative device architectures.
As a result, algorithmic hardware designers using ESL tools consistently achieve better results than hand-coded methodologies or hard IP, and achieve these results in days rather than months for many data path intensive designs.
In addition to dramatic design quality improvements, an ESL design flow can result in 60 per cent fewer bugs.
During simulation, advanced ESL tools can automatically create SystemC transaction-level models and wrappers, allowing designers to rapidly explore architectural tradeoffs and simulate their designs 20-100 times faster than traditional RTL using verification environments that support SystemC. With the ability to generate SystemC models, designers can rapidly explore architectural tradeoffs and verify designs, while re-using existing C++ testbenches throughout.
The early adopters of ESL are clustered around high-pain application segments, specifically in the burgeoning consumer and communications sectors which are well suited to higher-level synthesis.
The question of whether ESL is right for you depends, of course, on design requirements. If you need to accelerate hardware development, you may be a very good candidate. If you need to perform architectural analysis with performance models, then you should definitely consider ESL. It can be a powerful aid in quickly getting a data intensive design to market on an aggressive schedule.
Whether or not you have used ESL design tools please take a minute to fill out the online ESL survey at www.mentorgraphics.de/esl-survey.
The results will be publicised in Electronics Weekly in early 2006 and should provide some idea about how people view the key questions of ESL adoption and implementation.
Simon Bloch is general manager, Design Creation & Synthesis Division, Mentor Graphics
www.mentor.com