Bringing parallel processing to the place and route of ICs saves a massive amount of time, according to Mentor Graphics which has just produced a tool which can spread the place and router load over a number of cores.
According to Sudhakar Jilla, director of Mentor's place and route group, customers are saying that distributing the task between eight cores take between six to eight weeks off a typical four to six month IC design cycle.
Mentor claims that parallel processing can speed up design closure times by four times on an eight core machine and speed up timing analysis on an eight core machine.
A customer's 150m gate 40nm design took 12 hours instead of three and a half days, said Jilla, and NEC reported a four times reduction in design closure time on a 30m gate, four mode four corner IC using the Mentor parallel processing tool which is called Olympus.
According to Mentor, 70 per cent of the place and route runtime is in timing analysis and optimisation phases. What Mentor has parallelised is the timing analysis and optimisation phases.
The cleverness of the Mentor tool is that it can distribute the tasks involved in these phases almost equally across the available cores so that the performance of the tool scales almost linearly with the number of cores.
So, on eight cores, the tool will deliver seven times more performance than one core and on 16 cores it will deliver 13 times the performance.
Although it has only been run, so far, on x86 cores from Intel and AMD the tool can be run on any core.
"It's not tied to any one architecture per se", said Jilla, "we just see cores as something to dump your tasks on." So you could use a SPARC, a MIPS, a Cell, or a PowerPC if you wanted to.
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