Toshiba’s foundry business is offering system-in-package (SiP) devices with integrated RF circuits and digital CMOS down to 40nm process nodes.
For the RF Process Design Kit (PDK), 130nm, 90nm and 65nm processes are characterised by transistor F(t)s of 90GHz, 140GHz and 180GHz respectively.
The RF module also offer on-chip integration of passive elements such as MIM capacitors; junction and mosfet varactors (deep N-well, single-end and differential); half-turn differential or symmetrical inductors; and mid-range poly resistors with zero temperature coefficients.
Junction capacitors and parasitic devices such as NPN transistors are also available.
To support development Toshiba is offering a ‘hybrid’ ASIC / COT model flow which includes the digital baseband processor and the other for the analogue and RF elements.
For the RF- and analogue elements, the customer implements the GDSII based on the RF-PDK.
Once the macro cell layout is frozen, all manufacturability and yield-assurance rules will have been followed, and downstream re-spins avoided.
For the digital portion of the chip, an RT-level or gate-level netlist is accepted and the GDSII for the digital portion is implemented by Toshiba, as in a standard ASIC flow.
Standard ASIC libraries, SPICE DFM/DFY models and package parasitics are part of the design environment.
The analogue or RF blocks are finally integrated into the top-level layout. After the SoC layout is complete, the customer signs the project off based on the verification reports provided.