Xilinx is claiming faster FPGA development times with the latest release of its ISE Design Suite.
Now in version 10.1, the suite consists of separate tools supporting not only FPGA logic designs, but also embedded and DSP designs. For the first time these will be made available at one time.
Xilinx has tuned its design algorithms to improve the placement of large logic blocks and the placement of buses. “We see an average of x2 improvement in runtime due to tuning the algorithm,” Giles Peckham, marketing manager in the comms group at Xilinx told EW.
The FPGA company has also looked at t eh way very complex design can be carried out on a number of machines. A feature called SmartXplorer, allows the tool to be used across a number of Linux-based machines so that complex designs can be carried out in less time. “This can result in 38 per cent faster implementations,” said Peckham.
There is an improved XPower power analysis tool and a streamlined version of the PlanAhead floorplanner which includes a new type of intuitive pinout tool called PinAhead (picture).
Once the pin assignments have been completed, PinAhead will export I/O port information through either comma separated value (CSV) files or via VHDL or Verilog headers.
www.xilinx.com/ISE